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Page 119
TMP86CH09NG
11.7 Interrupt Generation
The SEI for the TMP86CH09NG uses INTSEI1. When the SESR<SEF> changes state from “0” to “1”, respective
interrupts is generated.
11.8 SEI System Errors
The SEI has the facility to detect following two system errors.
Write collision error:
When the SEDR register is accessed for write during transfer.
Overflow error:
When the new data byte is shift in before the previous data byte is read in slave mode.
11.8.1 Write collision error
Collision of writes occurs when an attempt is made to write to the SEDR register while transfer is in
progress. Because the SEDR register is not configured as dual-buffers when sending data, a write to the SEDR
register directly results in writing to the SEI shift register. Therefore, writing to the SEDR register while trans-
fer is in progress causes a write collision error.
In no case is data transfer stopped in the middle, so that the write data which caused a write collision error
will not be written to the shift register. Because slaves cannot control the timing at which the master starts a
transfer, collision of writes normally occurs on the slave side.
Write collision errors do not normally occur on the master side because the master has the right to perform a
transfer at any time, but in view of SEI logic both the master and slaves have the facility to detect write colli-
sion errors.
A write collision error tends to occur on the slave side when the master shifts out data at a speed faster than
that at which the slave processes the transferred data. More specifically, a write collision error occurs in cases
where the slave transfers a new value to the SEDR register when the master already started a shift cycle for the
next byte.
11.8.2 Overflow error
The transfer bit rate on the SEI bus is determined by the master. A high bit rate causes a problem that a slave
cannot keep abreast with transfer from the master, because the master is shifting out data faster than can be pro-
cessed by the slave. The SEI module uses the SOVF flag (SESR<SOVF>) to detect that data has overflowed.
The SOVF flag is set in the following cases:
When the SEI module is set for slave
When the old data byte remains to be read while a new data byte has been received
When the SOVF flag is set, the SEDR register is overwritten with a new data byte.
Note:Please carefully examine the communication processing routine and communication rate when designing
your application system.
Table 11-6 SEI Interrupt
SEI interrupt channel 1 (INTSEI1)
Interrupt generated for SEF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMP86FH09NG(ZM) | 功能描述:8位微控制器 -MCU TLCS870/C 16K FLASH RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| TMP86FH12MG | 制造商:Toshiba America Electronic Components 功能描述:MCU 8BIT TLCS-870 CISC 16KB FLASH 5V 30SSOP - Bulk 制造商:Toshiba America Electronic Components 功能描述:8BIT MCU 16K FLASH 512B RAM 86FH12 |
| TMP86FH12MG(Z) | 功能描述:8位微控制器 -MCU 16k Flash MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| TMP86FH46ANG | 制造商:Toshiba America Electronic Components 功能描述:MCU 8BIT TLCS-870 CISC 16KB FLASH 5V 42PIN SDIP - Bulk |
| TMP86FH46ANG(Z) | 功能描述:8位微控制器 -MCU 16K Flash MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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