參數(shù)資料
型號: TMP86FH09NG
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PDIP32
封裝: 0.400 INCH, 1.78 MM PITCH, LEAD FREE, PLASTIC, SDIP-32
文件頁數(shù): 27/154頁
文件大?。?/td> 1433K
代理商: TMP86FH09NG
Page 112
11. Serial Expansion Interface (SEI)
11.2 SEI Registers
TMP86CH09NG
11.2 SEI Registers
The SEI interface has the SEI Control Register (SECR), SEI Status Register (SESR), and SEI Data Register
(SEDR) which are used to set up the SEI system and enable/disable SEI operation.
11.2.1 SEI Control Register (SECR)
11.2.1.1 Transfer rate
(1) Master mode (Transfer rate = fc/Internal clock divide ratio (unit : bps))
The table below shows the relationship between settings of the SER bit and transfer bit rates when
the SEI is operating as the master.
76
54321
0
SECR
(002AH)
MODE
SEE
BOS
MSTR
CPOL
CPHA
SER
(Initial value: 0000 0100)
Read-modify-write instruction are prohibited
MODE
Mode fault detection#1
#1
If mode fault detection is enabled, an interrupt is generated when the MODF flag (SESR<MODF>) is set.
0: Enables mode fault detection
1: Disables mode fault detection
It is available in Master mode only.
(Note: Make sure to set <MODE> bit to "1" for disabling Mode fault
detection
R/W
SEE
SEI operation#2
#2
SEI operation can only be disabled after transfer is completed. Before the SEI can be used, the each Port
Control Register and Output Latch Control must be set for the SEI function (In case P0 port, P0OUTCR and
P0DR).
When using the SEI as the master, set the SECR<SEE> bit to “1” (to enable SEI operation) and then place
transmit data in the SEDR register. This initiates transmission/reception.
0: Disables SEI operation
1: Enables SEI operation
BOS
Bit order selection
0: Transmitted beginning with the MSB (bit 7) of SEDR register
1: Transmitted beginning with the LSB (bit 0) of SEDR register
MSTR
Mode selection#3
#3
Master/slave settings must be made before enabling SEI operation (This means that the SECR<MSTR> bit
must first be set before setting the SECR<SEE> bit to “1”).
0: Sets SEI for slave
1: Sets SEI for master
CPOL
Clock polarity
0: Selects active-“H” clock. SCLK remains “L” when IDLE.
1: Selects active-“L” clock. SCLK remains “H” when IDLE.
CPHA
Clock phase
Selects clock phase. For details, refer to Section “SEI Transfer For-
mats”.
SER
Selects SEI transfer rate
00: Divide-by-4
01: Divide-by-8
10: Divide-by-16
11: Divide-by-64
Table 11-1 SEI Transfer Rate
SER
Internal Clock Divide Ratio of SEI
Transfer Rate when fc = 16 MHz
00
4
4 Mbps
01
8
2 Mbps
10
16
1 Mbps
11
64
250 kbps
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