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參數資料
| 型號： | TMP470R1B768PGE |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16/32-Bit RISC Flash Microcontroller |
| 中文描述： | 16/32位RISC閃存微控制器 |
| 文件頁數： | 5/50頁 |
| 文件大小： | 393K |
| 代理商： | TMP470R1B768PGE |
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Device Characteristics
Table 1
identifies all the characteristics of the TMS470R1B768 device except the SYSTEM and CPU, which are
generic.
TMS470R1B768
16/32-Bit RISC Flash Microcontroller
SPNS108A–AUGUST 2005–REVISED AUGUST 2006
Table 1. Device Characteristics
DEVICE DESCRIPTION
TMS470R1B768
CHARACTERISTICS
COMMENTS For B768
MEMORY
For the number of memory selects on this device, see
Table 3
,
Memory Selection Assignment
.
INTERNAL MEMORY
Pipeline/Non-Pipeline
768K-Byte flash
48K-Byte SRAM
Flash is pipeline-capable.
The B768 RAM is implemented in one 48K array selected by two
memory-select signals (see
Table 3
,
Memory Selection
Assignment
).
PERIPHERALS
For the device-specific interrupt priority configurations, see
Table 7
,
Interrupt Priority (IEM and CIM)
. And for the 1K peripheral address
ranges and their peripheral selects, see
Table 5
,
B768 Peripherals, System Module, and Flash Base Addresses
.
CLOCK
ZPLL
GENERAL-PURPOSE I/Os
15 I/O
1 Input only
ECP
YES
SCI
2 (3-pin)
CAN (HECC and/or SCC)
3 HECCs
SPI (5-pin, 4-pin or 3-pin)
5 (5-pin)
Zero-pin PLL has no external loop filter pins.
Port A has eight (8) external pins, port B has one (1), port C has
three (3), and port D has four (4).
SCI1 and SCI2
Three HECCs (HECC1, HECC2, and HECC3)
SPI1, SPI2, SPI3, SPI4, and SPI5
The B768 device has both the logic and registers for a full 32-I/O
HET implemented and all 32 pins are available externally.
The high-resolution (HR) SHARE feature allows even HR pins to
share the next higher odd HR pin structures. This HR sharing is
independent of whether or not the odd pin is available externally. If
an odd pin is available externally and shared, then the odd pin can
only be used as a general-purpose I/O. For more information on HR
SHARE, see the
TMS470R1x High-End Timer (HET) Refe4rence
Guide
(literature number SPNU199).
HET with XOR Share
32 I/O
HET RAM
128-Instruction Capacity
The B768 device has both the logic and registers for a full
16-channel MibADC implemented and all 16 pins are available
externally.
10-bit, 16-channel
256-word FIFO
MibADC
CORE VOLTAGE
I/O VOLTAGE
PINS
PACKAGE
1.81–2.05 V
3.0–3.6 V
144
PGE
5
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