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| 型號： | TMP470R1B768PGE |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16/32-Bit RISC Flash Microcontroller |
| 中文描述： | 16/32位RISC閃存微控制器 |
| 文件頁數(shù)： | 38/50頁 |
| 文件大?。?/td> | 393K |
| 代理商： | TMP470R1B768PGE |
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SPIn Slave Mode External Timing Parameters
(CLOCK PHASE = 1, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output)
(1)(2)(3)(4)
(see
Figure 15
)
TMS470R1B768
16/32-Bit RISC Flash Microcontroller
SPNS108A–AUGUST 2005–REVISED AUGUST 2006
Figure 14. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
NO.
MIN
MAX
UNI
T
ns
1
t
c(SPC)S
t
w(SPCH)S
t
w(SPCL)S
t
w(SPCL)S
t
w(SPCH)S
Cycle time, SPInCLK
(5)
Pulse duration, SPInCLK high (clock polarity = 0)
Pulse duration, SPInCLK low (clock polarity = 1)
Pulse duration, SPInCLK low (clock polarity = 0)
Pulse duration, SPInCLK high (clock polarity = 1)
Valid time, SPInCLK high after SPInSOMI data valid
(clock polarity = 0)
Valid time, SPInCLK low after SPInSOMI data valid
(clock polarity = 1)
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
Setup time, SPInSIMO before SPInCLK high
(clock polarity = 0)
Setup time, SPInSIMO before SPInCLK low
(clock polarity = 1)
100
256t
c(ICLK)
0.5t
c(SPC)S
– 0.25t
c(ICLK)
0.5t
c(SPC)S
– 0.25t
c(ICLK)
0.5t
c(SPC)S
– 0.25t
c(ICLK)
0.5t
c(SPC)S
– 0.25t
c(ICLK)
0.5t
c(SPC)S
+ 0.25t
c(ICLK)
0.5t
c(SPC)S
+ 0.25t
c(ICLK)
0.5t
c(SPC)S
+ 0.25t
c(ICLK)
0.5t
c(SPC)S
+ 0.25t
c(ICLK)
2
(6)
ns
3
(7)
ns
t
v(SOMI-SPCH)S
0.5t
c(SPC)S
– 6 – t
r
4
(7)
ns
t
v(SOMI-SPCL)S
0.5t
c(SPC)S
– 6 – t
f
t
v(SPCH-SOMI)S
0.5t
c(SPC)S
– 6 – t
r
5
(7)
ns
t
v(SPCL-SOMI)S
0.5t
c(SPC)S
– 6 – t
f
t
su(SIMO-SPCH)S
6
6
(6)
ns
t
su(SIMO-SPCL)S
6
(1)
(2)
(3)
(4)
(5)
The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.
If the SPI is in slave mode, the following must be true: t
≥
(PS + 1) t
, where PS = prescale value set in SPInCTL1[12:5].
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
t
= interface clock cycle time = 1/f
When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: t
c(SPC)S
≥
(PS +1)t
c(ICLK)
≥
100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: t
= 2t
≥
100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
(6)
(7)
38
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