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SPIn Master Mode External Timing Parameters
(CLOCK PHASE = 1, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input)
(1)(2)(3)
(see
Figure 13
)
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TMS470R1B768
16/32-Bit RISC Flash Microcontroller
SPNS108A–AUGUST 2005–REVISED AUGUST 2006
NO.
1
MIN
100
MAX
UNIT
ns
t
c(SPC)M
t
w(SPCH)M
t
w(SPCL)M
t
w(SPCL)M
t
w(SPCH)M
Cycle time, SPInCLK
(4)
Pulse duration, SPInCLK high (clock polarity = 0)
Pulse duration, SPInCLK low (clock polarity = 1)
Pulse duration, SPInCLK low (clock polarity = 0)
Pulse duration, SPInCLK high (clock polarity = 1)
Valid time, SPInCLK high after SPInSIMO data valid
(clock polarity = 0)
Valid time, SPInCLK low after SPInSIMO data valid
(clock polarity = 1)
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 1)
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 0)
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 1)
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
256t
c(ICLK)
0.5t
c(SPC)M
+ 5
0.5t
c(SPC)M
+ 5
0.5t
c(SPC)M
+ 5
0.5t
c(SPC)M
+ 5
0.5t
c(SPC)M
– t
r
0.5t
c(SPC)M
– t
f
0.5t
c(SPC)M
– t
f
0.5t
c(SPC)M
– t
r
2
(5)
ns
3
(5)
ns
t
v(SIMO-SPCH)M
0.5t
c(SPC)M
– 15
4
(5)
ns
t
v(SIMO-SPCL)M
0.5t
c(SPC)M
– 15
t
v(SPCH-SIMO)M
0.5t
c(SPC)M
– 5 – t
r
5
(5)
ns
t
v(SPCL-SIMO)M
0.5t
c(SPC)M
– 5 – t
f
t
su(SOMI-SPCH)M
6
6
(6)
ns
t
su(SOMI-SPCL)M
6
t
v(SPCH-SOMI)M
4
7
(6)
ns
t
v(SPCL-SOMI)M
4
(1)
(2)
(3)
(4)
The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.
t
= interface clock cycle time = 1/f
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: t
c(SPC)M
≥
(PS +1)t
c(ICLK)
≥
100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: t
= 2t
≥
100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
(5)
(6)
Figure 13. SPIn Master Mode External Timing (CLOCK PHASE = 1)
36
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