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TMS470R1B768
16/32-Bit RISC Flash Microcontroller
SPNS108A–AUGUST 2005–REVISED AUGUST 2006
Table 2. Terminal Functions (continued)
TERMINAL
INTERNAL
PULLUP/
PULLDOWN
(3)
TYPE
(1)(2)
DESCRIPTION
NAME
NO.
TEST/DEBUG (T/D) (CONTINUED)
Test enable. Reserved for internal use only. TI recommends that this pin be
IPD (20 μA)
connected to ground or pulled down to ground by an external resistor.
Serial input for controlling the state of the CPU test access port (TAP)
IPU (20 μA)
controller (JTAG)
Serial input for controlling the second TAP. TI recommends that this pin be
IPU (20 μA)
connected to V
CCIO
or pulled up to V
CCIO
by an external resistor.
Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG)
IPD (20 μA)
Boundary-Scan Logic. TI recommends that this pin be pulled down to ground
by an external resistor.
FLASH
Flash test pad 1.
For proper operation, this pin must not be connected
[no connect (NC)].
Flash test pad 2.
For proper operation, this pin must not be connected
[no connect (NC)].
Flash external pump voltage (3.3 V). This pin is required for both flash read
and flash program and erase operations.
SUPPLY VOLTAGE CORE (1.8 V)
TEST
38
3.3-V I
TMS
120
3.3-V I
TMS2
121
3.3-V I
TRST
37
3.3-V I
FLTP1
134
NC
FLTP2
133
NC
V
CCP
135
3.3-V PWR
14
31
55
86
93
128
132
V
CC
1.8-V PWR
Core logic supply voltage
SUPPLY VOLTAGE DIGITAL I/O (3.3 V)
17
53
82
V
CCIO
3.3-V PWR
Digital I/O supply voltage
SUPPLY GROUND CORE
11
30
54
85
92
127
131
136
V
SS
GND
Core supply ground reference
SUPPLY GROUND DIGITAL I/O
16
52
81
V
SSIO
GND
Digital I/O supply ground reference
11
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