參數(shù)資料
型號: TMC2193KJC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 消費家電
英文描述: 10 Bit Encoder
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: MQFP-100
文件頁數(shù): 50/72頁
文件大?。?/td> 448K
代理商: TMC2193KJC
TMC2193
PRODUCT SPECIFICATION
50
REV. 1.0 3/26/03
Control Register De
fi
nitions
(continued)
Closed Caption Register (0x1D)
7
6
5
4
3
2
1
0
CCD2
Reg
1D
Bit
7-0
Name
CCD2
Description
Second Byte of CC Data.
Bit 0 is the LSB. The MSB will be overwritten by an ODD Parity Bit if
CCPAR is HIGH
Closed Caption Register (0x1E)
7
6
5
4
3
2
1
0
CCON
CCRTS
CCPAR
CCFLD
CCLINE
Reg
1E
Bit
7
Name
CCON
Description
Enable CC Data Packet.
Command the CC data generator to send either CC data or a NULL byte
whenever the specified line is transmitted.
Request To Send Data.
This bit is set HIGH by the user when bytes 0x1C and 0x1D have been
loaded with the next two bytes to be sent. When the encoder
s line count
reaches preceding the line specified in bits 4-0 of this register the data will
be transferred from registers 0x1C and 0x1D, and RTS will be RESET
LOW. A new pair of bytes may then be loaded into registers 0x1C and
0x1D. If CCON = 1 and CCRTS = 0 when the CC line is to be sent, NULL
bytes will be sent.
Auto Parity Generation.
When set HIGH, the encoder replaces the MSB of bytes 0x1C and 0x1D
with a calculated ODD parity. When set LOW, the CC processor transmits
the 16 bits exactly as loaded into registers 0x1C and 0x1D.
CC Field Select.
When LOW, CC data is transmitted on the selected line of ODD fields.
When HIGH, it is sent on EVEN fields.
CC Line Select.
Defines (with an offset) the line on which CC data are transmitted.
1E
6
CCRTS
1E
5
CCPAR
1E
4
CCFLD
1E
3-0
CCLINE
Timing Register (0x1F)
7
6
5
4
3
2
1
0
PDCNT
Reg
1F
Bit
7-0
Name
PDCNT
Description
Pixel Data Control Start.
PDCNT determines the number of pixels (PCK
s) from the midpoint of the
falling edge of horizontal sync to the rising edge of PDC on active video
lines.
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