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參數(shù)資料
| 型號： | TMC2193KJC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 10 Bit Encoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 31/72頁 |
| 文件大?。?/td> | 448K |
| 代理商： | TMC2193KJC |
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PRODUCT SPECIFICATION
TMC2193
REV. 1.0 3/26/03
31
relation to the PD port. Control register OMIX chooses
among the following set of coefficients; either 0 1/8 1/2 7/8
1, 0 1/2 1 , or 0 1 to switch between the PD port and the over-
lay color. The timing diagram in Figure 22 identifies the
three possible output formats that the mixer can produce.
Figure 22. Overlay Outputs
Hardware Keying
The KEY input switches the input to the Comp2 data path
between the composite video generated from the PD port and
the CVBS data bus on a pixel-by-pixel basis. This is a “soft”
switch is executed over 3 PCK periods to minimize out-of-
band transients. Keying is accomplished in the digital com-
posite video domain. The coefficients for the mix are 0, 1/8,
1/2, 7/8, and 1 . The COMP2 output is the final output for all
overlay functions. The other three D/As will continue to
present PD port data when CVBS is active.
Hardware keying is enabled by the key Control Register
HKEN. Normally, keying is only effective during the active
video portion of the encoded video line (as determined by
Control Register VA). That is, the horizontal blanking inter-
val is generated by the encoder even if the KEY signal is
held HIGH through horizontal blanking. However, it is pos-
sible to allow digital horizontal blanking to be passed
through from the CVBS bus to the COMP2 output by setting
key Control Register BUKEN HIGH. In this mode, KEY is
always active, and may be exercised at will.
The KEY input is registered into the encoder just as Pixel
data is clocked into the PD port. It is internally pipelined, so
the midpoint of the KEY transition occurs at the output of
the pixel that was input at the same time at the KEY signal.
Data Keying
Data Keying occurs just prior to the gamma block. Data key-
ing for each channel Green/Y, Blue/C
b
, and Red/C
r
, is sepa-
rately enabled or disabled by the control registers
DKEYDIS, EKEYDIS, and FKEYDIS. On each channel the
eight (8) MSBs of the pixel data are compared against a
maximum key value and a minimum key value. If the pixel
data is greater than xKEYMIN and less than or equal to
xKEYMAX, then a key match is signaled for that channel.
Figure 23. Data Keying
By allowing a window of possible key values on each chan-
nel the TMC2193 opens a key cube in the color space.
Parallel Microprocessor Interface
The parallel microprocessor interface is active when SER is
HIGH and employs a 12-line interface; an 8 bit data bus and
2 bit address location, 1 bit read/write select, and a chip
select controlling the timing. Two addresses are required for
device programming, one to the pointer and one to the data
location. When writing, the address is presented along with a
LOW on the R/W pin during the falling edge of CS. Eight
bits of data are presented on D7-0 during the subsequent ris-
ing edge of CS.
Table 23. Overlay Address Map
OL4-0
0
1-15
16
17-31
Result
Pixel data is passed through overlay mixer.
Overlay is mixed with PD or CVBS at the transitions.
Half amplitude PD or half amplitude CVBS is the output of COMP2.
Overlay is mixed with half amplitude PD or half amplitude CVBS at the transitions.
A
A
>0
0
OL[4:0]
B
C
D
E
F
G
H
I
PDx
A
B
OL
OL
OL
I
OL
OL
H
A
B
1/2C, 1/2OL
OL
OL
I
OL
1/2G, 1/2OL
H
MixOUT (OMIX = 3)
A
7/8B, 1/8OL 1/2C, 1/2OL 1/8D, 7/8OL
OL
I
1/8F, 7/8OL 1/2G, 1/2OL 7/8H, 1/8OL
MixOUT (OMIX = 2)
MixOUT (OMIX = 1)
65-6294-24
xKEYMAX
A<=B
A
B
A<=B
A
B
KEY
MATCH
xKEYMIN
xCHANNEL
65-6294-25
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