參數(shù)資料
型號： TMC2193KJC
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 消費(fèi)家電
英文描述： 10 Bit Encoder
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： MQFP-100
文件頁數(shù)： 30/72頁
文件大小： 448K
代理商： TMC2193KJC
TMC2193
PRODUCT SPECIFICATION
30
REV. 1.0 3/26/03
Layering Engine
Control Registers for this section
The TMC2193 features a robust layering engine with three
possible input layers controlled by two keying controls. The
layer assignments are shown in Table 22, along with the key-
ing control. The keying controls, KEY pin or OL4-0 are
aligned with the incoming pixel data stream and are then
delayed throughout the chip to be continuously aligned with
the input video streams. A generic overview of the keying
and layering features is shown in Figure 21.
Figure 21. Layering Engine
Overlay Mixer
The OL[4:0] bus provides the ability to overlay 30 different
24 bit values onto the pixel data path. The 24 bit overlay col-
ors must be the same format as the incoming Pixel data. For
Y,Cb,Cr input formats the range of Y values spans the entire
range of the format, 1 to 254, this enables super whites and
super blacks in the overlay palette.
When OL[4:0] is equal to 00h the pixel data port to be the
output of the overlay mixer. If OL[4:0] is in the range of 1 to
31 then the output source is one of 30 possible overlay col-
ors, see Table 22. Overlay Address Map. When OL4-0 equal
to 16, the overlay mixer produces a pixel data output with
half the luminance magnitude and chrominance magnitude.
Any OL4-0 value greater than 16 will result in a overlay mix
with a full amplitude overlay and the pixel data with half
amplitude pixel data (PD) or half amplitude CVBS data as its
values. This allows for transparent overlays or produce
shadow boxes around overlaid text.
The midpoint of the rising and falling edges on the mixed
output is determined by the transition of the OL[4:0] pins in
Address
0x04
0x05
0x07
0x09
0x09
0x09
0x09
0x09
0x09
0x09
Bit(s)
2
3-2
6
7
6
5
4
3
2
1-0
Name
SKEN
OMIX
SKFLIP
HKEN
BUKEN
SKEXT
DKDIS
EKDIS
FKDIS
LAYMODE
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
7-0
7-0
7-0
7-0
7-0
7-0
DKEYMAX
DKEYMIN
EKEYMAX
EKEYMIN
FKEYMAX
FKEYMIN
Address
Bit(s)
Name
Table 22. Layering and Keying Modes
LAYMODE
BACKGROUND
Image Source
PD
PD
CVBS
CVBS
MIDGROUND
FOREGROUND
Image Source
OVERLAY
CVBS
OVERLAY
PD
Keying Control
OL4-0
KEY or Data Key
OL4-0
KEY or Data Key
Image Source
CVBS
OVERLAY
PD
OVERLAY
Keying Control
KEY or Data Key
OL4-0
KEY or Data Key
OL4-0
0
1
2
3
PD
DATA KEY
KEY
OVERLAY
MIXER
OLUT
OL4-0
KEYING
MIXER
CVBS
PD
YC
dT
dT
dT
dT
dT
dT
dT
COMP2
LOGIC
LOGIC
1/2AMP
65-6294-23
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