參數(shù)資料
型號： TMC2193KJC
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 消費家電
英文描述： 10 Bit Encoder
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： MQFP-100
文件頁數(shù)： 3/72頁
文件大?。?/td> 448K
代理商： TMC2193KJC
PRODUCT SPECIFICATION
TMC2193
REV. 1.0 3/26/03
3
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Input Formats . . . . . . . . . . . . . . . . . . . . . .7
24 bit Input Format . . . . . . . . . . . . . . . . . .7
CCIR656 Input Format . . . . . . . . . . . . . . .8
10 bit Input Format . . . . . . . . . . . . . . . . . .8
20 bit 4:2:2 Input Format . . . . . . . . . . . . .8
20 bit 4:4:4 Input Format . . . . . . . . . . . . .8
Gamma Curves . . . . . . . . . . . . . . . . . . . .9
Propagation Delay through the
Encoder . . . . . . . . . . . . . . . . . . . . . . . . .12
Horizontal Timing . . . . . . . . . . . . . . . . . .15
Figure 10. Horizontal Timing – Vertical Blanking . . .15
Figure 11. Horizontal Timing – 1st Half-line. . . . . . .16
Figure 12. Horizontal Timing – 2nd Half-line . . . . . .16
Figure 13. NTSC Vertical Interval . . . . . . . . . . . . . .17
Figure 14. PAL Vertical Interval . . . . . . . . . . . . . . . .19
Figure 15. PAL-M Vertical Interval . . . . . . . . . . . . . .21
Figure 16. Burst Envelope . . . . . . . . . . . . . . . . . . . .25
Figure 17. Gaussian Filter Response . . . . . . . . . . .25
Figure 18. Interpolation Filter. . . . . . . . . . . . . . . . . .27
Figure 19. Interpolation Filter – Passband
Detail . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 20. X/SIN(X) Filter . . . . . . . . . . . . . . . . . . . .27
Figure 21. Layering Engine . . . . . . . . . . . . . . . . . . .30
Figure 22. Overlay Outputs . . . . . . . . . . . . . . . . . . .31
Figure 23. Data Keying . . . . . . . . . . . . . . . . . . . . . .31
Figure 24. Microprocessor Parallel Port –
Write Timing . . . . . . . . . . . . . . . . . . . . . .32
Figure 25. Microprocessor Parallel Port –
Read Timing . . . . . . . . . . . . . . . . . . . . . .32
Figure 26. Serial Port Read/Write Timing . . . . . . . .33
Figure 27. Serial Interface – Typical Byte
Transfer. . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 28. Serial Interface – Chip Address . . . . . . .34
Figure 29. Typical Analog Reconstruction Filter . . .65
Figure 30. Overall Response. . . . . . . . . . . . . . . . . .65
Figure 31. Typical Layout. . . . . . . . . . . . . . . . . . . . .67
Figure 32. ST-163E Layout . . . . . . . . . . . . . . . . . . .68
Figure 33. Pass Band . . . . . . . . . . . . . . . . . . . . . . .69
Figure 34. Stop Band. . . . . . . . . . . . . . . . . . . . . . . .69
Figure 35. 2T Pulse . . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 36. Group Delay . . . . . . . . . . . . . . . . . . . . . .69
Figure 9.
List of Tables
Table 1.
Table 2.
CSM Coefficient Range . . . . . . . . . . . . 10
Expected Output Values for the
CSM with YCBCR Inputs . . . . . . . . . . . 11
Expected Output Values for the
CSM with RGB Inputs. . . . . . . . . . . . . . 11
Coefficient sets YCBCR inputs. . . . . . . 11
Coefficient sets YCBCR inputs. . . . . . . 11
PDC Edge Control . . . . . . . . . . . . . . . . 13
Horizontal Line Equations. . . . . . . . . . . 14
Horizontal Timing Specifications. . . . . . 15
Vertical Interval Timing
Specifications . . . . . . . . . . . . . . . . . . . . 16
Default Horizontal Timing
Parameters. . . . . . . . . . . . . . . . . . . . . . 17
NTSC Field/Line Sequence and
Identification . . . . . . . . . . . . . . . . . . . . . 18
PAL Field/Line Sequence and
Identification . . . . . . . . . . . . . . . . . . . . . 20
PAL-M Field/Line Sequence and
Identification . . . . . . . . . . . . . . . . . . . . . 22
Standard Subcarrier Parameters . . . . . 24
Line by Line Pedestal Enable . . . . . . . . 25
Closed Caption Line Selection . . . . . . . 26
D/A Outputs . . . . . . . . . . . . . . . . . . . . . 27
Ancillary Data Format. . . . . . . . . . . . . . 28
Ancillary Data Control – Phase . . . . . . 29
Ancillary Data Control Frequency. . . . . 29
Field Identification and Subcarrier
Reset Modes . . . . . . . . . . . . . . . . . . . . 29
Layering and Keying Modes . . . . . . . . . 30
Overlay Address Map. . . . . . . . . . . . . . 31
Parallel Port Control . . . . . . . . . . . . . . . 32
Serial Port Addresses. . . . . . . . . . . . . . 33
Control Register Map . . . . . . . . . . . . . . 35
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
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