參數(shù)資料
型號(hào)： TMC2072
廠商： Fairchild Semiconductor Corporation
英文描述： Genlocking Video Digitizer
中文描述： 同步鎖相視頻數(shù)字化儀
文件頁(yè)數(shù)： 7/21頁(yè)
文件大?。?/td> 160K
代理商： TMC2072
PRODUCT SPECIFICATION
TMC2072
REV. 1.0.4 6/19/01
7
RESET
7
TTL
Master reset input.
Bringing RESET LOW forces the internal state
machines to their starting states, loads the Control Register with
default values, and disables outputs. Bringing RESET HIGH restarts
the TMC2072 in its default mode.
Interrupt output.
This output is LOW if the internal horizontal phase
lock loop is unlocked with respect to incoming video for 128 or more
lines per field. After lock is established, INT goes HIGH.
HSYNC locked flag.
Hsync locked flag. When high, this output
indicates that the most recent incoming horizontal sync has been
detected within ±16 pixels of its expected position. It goes low if no
sync is encountered during this ±16-pixel window, as during a
typical VCR headswitch line. Once the chip has locked to a clean
video source, this flag should remain high continuously. If the chip
has locked to a VCR, this flag will typically go low for one (or
sometimes two) lines at the bottom of each field.
Burst lock flag
. When high, this output indicates that the chip
’
s
internal
subcarrier synthesizer is phase-aligned
with the current
line
’
s incoming chroma burst. The flag goes low when the internal
and external phases diverge.
INT
17
TTL
VALID
34
TTL
BURL
31
TTL/
CMOS
Analog Interface
V
REF
70
+1.23 V
V
REF
input/output.
+1.23 Volt reference. When the internal voltage
reference is used, this pin should be decoupled to A
GND
with a 0.1
μ
F capacitor. An external +1.2 Volt reference may be connected
here, overriding the internal reference source.
Compensation capacitor.
Compensation for DDS D/A converter
circuitry. This pin should be decoupled to V
DDA
with a 0.1
μ
F
capacitor.
A/D V
REF
decoupling.
Decoupling points for A/D converter voltage
references. These pins should be decoupled to A
GND
with a 0.1
μ
F
capacitor.
COMP
88
0.1
μ
F
R
B
, R
T
57, 68
0.1
μ
F
PLL Filter
DDS OUT
82
Internal DDS output.
Analog output from the internal Direct Digital
Synthesizer D/A converter, at 1/9 the PXCK frequency.
Horizontal PLL input.
Analog input to the Phase/Frequency
Detector of the horizontal phase-locked loop.
Comparator bypass.
Decoupling point for the internal comparator
reference of the Phase/Frequency Detector. This pin should be
decoupled to A
GND
with a 0.1
μ
F capacitor.
PFD IN
77
C
BYP
75
1
μ
F
Power Supply
V
DDA
49, 51, 52, 60,
64, 73, 87
6, 18, 26, 42, 44,
48, 92, 98, 100
+5 V
Analog power supply.
Positive power supply to analog section.
All pins must be connected.
Digital power supply.
Positive power supply to digital section.
All pins must be connected.
V
DD
+5 V
Ground
A
GND
50, 55, 63, 67,
69, 72, 74, 81, 89
8, 16, 27, 38, 39,
41, 46, 47, 90,
95-97
0.0 V
Analog ground.
Ground for analog section. All pins must be
connected.
Digital ground.
Ground for digital section. All pins must be
connected.
D
GND
0.0 V
Pin De
fi
nitions
(continued)
Pin Name
Pin Number
Pin Type
Function
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