參數(shù)資料
型號(hào)： TMC2072
廠商： Fairchild Semiconductor Corporation
英文描述： Genlocking Video Digitizer
中文描述： 同步鎖相視頻數(shù)字化儀
文件頁(yè)數(shù)： 3/21頁(yè)
文件大?。?/td> 160K
代理商： TMC2072
PRODUCT SPECIFICATION
TMC2072
REV. 1.0.4 6/19/01
3
If incoming video is lost or disconnected after the TMC2072
has locked to it, PXCK and GRS data will continue, but
GVSYNC and every eighth GHSYNC will cease until lock
is reestablished. The GRS will report the initial subcarrier
frequency set by the Format select bits of the Control
Register. The TMC2072 will relock to incoming video
within two frames after it is restored.
Subcarrier Phase-Locked Loop
A fully-digital phase-locked loop is used to extract the phase
and frequency of the incoming color burst. These frequency
and phase values are output over the CVBS bus during the
horizontal sync period. Fairchild’s video decoder and gen-
lockable encoder chips will accept these data directly.
Back Porch Digital Clamp
A digital back-porch clamp is employed to ensure a constant
blanking level. It digitally offsets the data from the A/D con-
verter to set the back porch level to precisely 3C
h
for NTSC
and 40
h
for PAL. When the digital clamp is enabled, the
CVBS video output data is the A/D conversion result minus
the back porch level plus 3C
h
(40
h
for PAL). The back-porch
level is low-pass filtered to minimize streaking artifacts from
subtle line-to-line variations.
Digitized Video Output
The digitized 8-bit video output is provided over an 8-bit
wide CVBS data port, synchronous with PXCK and LDV.
Subcarrier frequency, subcarrier phase, and Field ID data
(GRS) are transmitted in 4-bit nibbles over CVBS
3-0
during
the horizontal sync tip period at the PXCK rate.
Microprocessor Interface
The TMC2072 is controlled by a standard 2-wire bus. Up to
eight TMC2072 devices may be connected to the 2-wire
serial interface with each device having a unique address.
The 2-wire interface comprises a clock input (SCL) and a
bi-directional data (SDA) pin. The TMC2072 acts as a slave
for receiving and transmitting data over the serial interface.
When the serial interface is not active, the logic levels on
SCL and SDA are pulled HIGH by external pull-up resistors.
Data received or transmitted on the SDA line must be stable
for the duration of the positive-going SCL pulse. Data on
SDA must change only when SCL is LOW. If SDA changes
state while SCL is HIGH, the serial interface interprets that
action as a start or stop sequence.
There are five components to serial bus operation:
Start signal
Slave address byte
Base register address byte
Data byte to read or write
Stop signal
When the serial interface is inactive (SCL and SDA are
HIGH) communications are initiated by sending a start sig-
nal. The start signal is a HIGH-to-LOW transition on SDA
while SCL is HIGH. This signal alerts all slaved devices that
a data transfer sequence is coming.
The first eight bits of data transferred after a start signal com-
prise a seven bit slave address and a single R/W bit. The R/W
bit indicates the direction of data transfer, read from or write
to the slave device. If the transmitted slave address matches
the address of the device (set by the state of the SA2:0 input
pins.), the TMC2072 acknowledges by bringing SDA LOW
on the 9th SCL pulse. If the addresses do not match, the
TMC2072 does not acknowledge.
Table 1. Serial Port Addresses
The address is 1000 SA
2
SA
1
SA
0
.
A
6
A
5
A
4
A
3
A
2
(SA
2
)
1/0
A
1
(SA
1
)
1/0
A
0
(SA
0
)
1/0
1
0
0
0
Figure 1. Microprocessor Parallel Port – Read Timing
t
PWLCS
t
PWHCS
t
SA
t
HA
SCL
SDA
SA
2
–SA
0
D
7
–D
0
t
DOM
t
DOM
t
DOZ
65-2072-02
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