參數(shù)資料
型號(hào)： TMC2072
廠(chǎng)商： Fairchild Semiconductor Corporation
英文描述： Genlocking Video Digitizer
中文描述： 同步鎖相視頻數(shù)字化儀
文件頁(yè)數(shù)： 19/21頁(yè)
文件大?。?/td> 160K
代理商： TMC2072
PRODUCT SPECIFICATION
TMC2072
REV. 1.0.4 6/19/01
19
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Wire-wrap is
not an option. Overall system performance is strongly influ-
enced by the board layout. Capacitive coupling from digital
to analog circuits may result in poor picture quality. Con-
sider the following suggestions when doing the layout:
1.
Keep the critical analog traces (COMP,V
REF
, R
T
, R
B
,
DDS OUT, PFD IN, C
BYP
, and V
IN1-3
) as short as pos-
sible and as far as possible from all digital signals. The
TMC2072 should be located near the board edge, close
to the analog output connectors.
2.
The digital power plane for the TMC2072 should be that
which supplies the rest of the digital circuitry. A single
power plane should be used for all of the V
DD
pins. If
the analog power supply for the TMC2072 is the same
as that of the system’s digital circuitry, power to the
TMC2072 V
DDA
pins should be decoupled with ferrite
beads and 0.1
μ
F capacitors to reduce noise.
3.
The ground plane should be solid, nor cross-hatched.
Connections to the ground plane should have very short
leads.
4.
Decoupling capacitors should be applied liberally to
V
DD
pins. Remember that not all power supply pins are
created equal. They typically supply adjacent circuits on
the device, which generate varying amounts of noise.
For best results, use 0.1
μ
F capacitors in parallel with
10
μ
F capacitors. Lead lengths should be minimized.
Ceramic chip capacitors are the best choice.
5.
If the digital power supply has a dedicated power plane
layer, it should not overlap the TMC2072, the voltage
reference or the analog outputs. Capacitive coupling of
digital power supply noise from this layer to the
TMC2072 and its related analog circuitry can degrade
performance.
6.
CLK should be handled carefully. Jitter and noise on
this clock or its ground reference may degrade perfor-
mance. Terminate the clock line carefully to eliminate
overshoot and ringing.
Related Products
TMC22x9x Digital Video Encoders
TMC2242/TMC2243/TMC2246 Video Filters
TMC2081 Digital Video Mixer
TMC22x5y Digital Decoders
TMC2302 Image Manipulation Sequencer
Interface to the TMC22x5y Decoder
The TMC22x5y Digital Video Decoders have been designed
to directly interface to the TMC2072 Digital Video Genlock.
The TMC2072 is the source for TMC22x9x input signals
CVBS
7-0
, GHSYNC, GVSYNC, LDV, and PXCK as shown
in Figure 20. These signals directly connect to the
TMC22x5y. The serial microprocessor interfaces for
TMC22x5y and TMC2072 are identical. The SDA and SCL
bus signals from the host microprocessor are shared by the
TMC22x5y and TMC2072. Only SA[2:0], VALID, and INT
signals are separate from the microprocessor bus.
Figure 20. TMC22x5y Interface Circuit
CVBS7:0
GHSYNC
GVSYNC
PXCK
R
S
S
LDV
65-2072-20
TMC2072
GENLOCKING VIDEO DIGITIZER
TMC22x5y
DIGITAL VIDEO DECODER
MICROPROCESSOR INTERFACE
8
CVBS7:0
GHSYNC
GVSYNC
PXCK
LDV
R
S
S
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