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參數(shù)資料
| 型號： | TMC2072 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Genlocking Video Digitizer |
| 中文描述： | 同步鎖相視頻數(shù)字化儀 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 160K |
| 代理商： | TMC2072 |
TMC2072
PRODUCT SPECIFICATION
10
REV. 1.0.4 6/19/01
Reg 0A Gain, loop
fi
lter, subpixel adjust
7
V_GAIN
Analog Gain into A/D Converter
. LOW (power-on default): unity gain, suitable
for nominal 1-volt (sync tip to reference white) video signals. HIGH: 1.5 X gain, for
over-terminated video signals with approximately 200mV sync tips. [TMC22071A
bit 9.]
Reserved
, test bit for DDSDAC; reset low (power-on default)
Horizontal Phase-Locked Loop Filter Bandwidth
. LOW (power-on default):
narrow H loop filter to minimize jitter with clean video sources. HIGH: wide filter
bandwidth, to better accommodate jittery or noisy sources.
Sample Clock (and Sync Signal) Subpixel Offset Timing Control
. Format is
fractional two
’
s complement, i.e., 0.SFFFF, where bit 4, the signed most
significant bit (S), represents 1 PXCK or 1/2 pixel. Thus, the programming range
is 01111 = +15/32 pixel to 10000 = -16/32 pixel. A value of 01000 will advance the
sample clock and syncs by 1/4 pixel relative to the incoming video, whereas a
value of 11000 will retard them the same amount. The power-on default value of
0 nominally aligns the sample clock with the center of the incoming signal
’
s falling
sync edges. [TMC22071A bits 16:12.]
6
5
DDS_TEST
HFILT
4:0
SUBPIX
Reg 0B Input select
7
6
5:4
Reserved
, reset low (power-on default)
Reserved
, test bit: noise comparator disable; reset low (power-on default)
These two bits determine which of the three analog input lines is active, as
follows:
NCOMP
SOURCE
00 VIN1 (power-on default)
01 VIN2
1X VIN3.
[TMC22071A bits 8:7.]
Reset low (power-on default) to compensate burst PLL for line-by-line changes in
sampling rate. Set high to disable compensation (test purpose only).
Reserved
, analog circuit test bits; reset low (power-on default)
Reg 0C Field and Vsync reporting
7
Reserved
, reset low (power-on default)
6
FID FREE
LOW (power-on default): The color frame identifier (FID[1] in NTSC) toggles
smoothly, but with no guaranteed relationship to the incoming color burst phase.
HIGH freezes FID[1] in NTSC mode, if a two-field (odd/even only) sequence is
desired.
5:3
Reserved
, reset low (power-on default)
2
DLYRPTF
Delay Field i.d. Update
. LOW (power-on default): FID will increment at the start
of each incoming vertical sync pulse group. (NTSC lines 4 and 266.) HIGH: FID
will increment at the start of the next line after the start each incoming vertical
sync.
1
DLYRPT
Delay GVSYNC Output
. LOW (power-on default): TMC2072 will generate a
GVSYNC falling edge as it predicts the start of a new vertical sync series. This is
recommended for laser disk or higher quality video signals, for which the chip can
easily predict video field timing. HIGH: TMC2072 will generate a GVSYNC falling
edge on the line after it detects the start of a vertical sync series. This is
recommended for jittery input signals, if a one-line upward image displacement is
acceptable.
3
SCALE
2:0
ANTEST
Details
(continued)
Bit
Name
Function
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2072_07 | 制造商:SMSC 制造商全稱:SMSC 功能描述:Peripheral Mode CircLink⑩ Controller |
| TMC2072KHC | 功能描述:視頻 IC Video Digitizer Genlocking RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TMC2072-MD | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Peripheral Mode CircLink Cntlr RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| TMC2072-MT | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Peripheral Mode CircLink Cntlr RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| TMC2074 | 制造商:SMSC 制造商全稱:SMSC 功能描述:Dual Mode CircLink⑩ Controller |
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