參數(shù)資料
型號: TEA5764HN
廠商: NXP SEMICONDUCTORS
元件分類: 接收器
英文描述: FM radio + RDS
中文描述: FM, AUDIO SINGLE CHIP RECEIVER, PQCC40
封裝: 6 X 6 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-618-1, HVQFN-40
文件頁數(shù): 33/64頁
文件大?。?/td> 287K
代理商: TEA5764HN
TEA5764HN_2
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 August 2005
33 of 64
Philips Semiconductors
TEA5764HN
FM radio + RDS
To speed up RDS traffic it is possible to read all the RDS data and then only write back
byte INTMSK to set the appropriate mask(s) again.
I
2
C-bus activity:
With bits PUPD the TEA5764HN can be switched in a low current Standby mode. The
I
2
C-bus is then still active
When the I
2
C-bus interface is deactivated, by making pin BUSENABLE LOW and
without programmed Standby mode, the TEA5764HN keeps its normal operation, but
is isolated from the I
2
C-bus lines
It is possible to operate the TEA5764HN with BUSENABLE hard wired to pin
VREFDIG, and have the bus interface always active.
t
f
= fall time of both SDA and SCL signals: 20 + 0.1 C
b
< t
f
< 300 ns, where C
b
= total capacitance on bus line in pF.
t
r
= rise time of both SDA and SCL signals: 20 + 0.1 C
b
< t
f
< 300 ns, where C
b
= total capacitance on bus line in pF.
t
HD;STA
= hold time (repeated) START condition. After this period, the first clock pulse is generated: > 600 ns.
t
HIGH
= HIGH period of the SCL clock: > 600 ns.
t
SU;STA
= setup time for a repeated START condition: > 600 ns.
t
HD;DAT
= data hold time: 300 < t
HD;DAT
< 900 ns.
Remark:
300 ns lower limit is added because the ASIC has no internal hold time for the SDA signal.
t
SU;DAT
= data setup time: t
SU;DAT
> 100 ns. If ASIC is used in a standard mode I
2
C-bus system, t
SU;DAT
> 250 ns.
t
SU;STO
= setup time for STOP condition: > 600 ns.
t
BUF
= bus free time between a STOP and a START condition: > 600 ns.
C
b
= capacitive load of one bus line: < 400 pF.
t
SU;BUSEN
= bus enable setup time: t
SU;BUSEN
> 10
μ
s.
t
HO;BUSEN
= bus enable hold time: t
HO:BUSEN
> 10
μ
s.
Fig 14. I
2
C-bus timing diagram
P
S
Sr
P
001aac796
t
HD;STA
t
BUF
t
SU;STA
t
SU;DAT
t
f
t
HIGH
t
LOW
t
SU;STO
t
r
t
HD;DAT
SDA
SCL
BUS
ENABLE
t
SU;BUSEN
t
HO;BUSEN
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