參數(shù)資料
型號： TE28F004B3T90
廠商： INTEL CORP
元件分類： DRAM
英文描述： 3 Volt Advanced Boot Block Flash Memory
中文描述： 512K X 8 FLASH 3V PROM, 90 ns, PDSO40
封裝： 10 X 20 MM, TSOP-40
文件頁數(shù)： 23/58頁
文件大?。?/td> 920K
代理商： TE28F004B3T90
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
3UHOLPLQDU\
17
3.6.1
RP# Connected to System Reset
The use of RP# during system reset is important with automated program/erase devices since the
system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. Intel recommends connecting RP# to the
system CPU RESET# signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when V
CC
voltages are above V
LKO
. Since
both WE# and CE# must be low for a command write, driving either signal to V
IH
will
inhibit
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until RP# is brought to V
IH
, regardless of the state of its control inputs.
By holding the device in reset (RP# connected to system POWERGOOD) during power-up/down,
invalid bus conditions during power-up can be masked, providing yet another level of memory
protection.
3.6.2
V
CC
, V
PP
and RP# Transitions
The CUI latches commands as issued by
system software and is not altered by V
PP
or CE#
transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after
V
CC
transitions above V
LKO
(Lockout voltage), is read array mode.
After any program or block erase operation is complete (even after V
PP
transitions down to
V
PPLK
), the CUI must be reset to read array mode via the Read Array command if access to the
flash memory array is desired.
3.7
Power Supply Decoupling
Flash memory’s power switching characteristics require careful device decoupling. System
designers should consider three supply current issues:
1. Standby current levels (I
CCS
)
2. Read current levels (I
CCR
)
3. Transient peaks produced by falling and rising edges of CE#.
Transient current magnitudes depend on the device outputs’ capacitive and inductive loading.
Two-line control and proper decoupling capacitor selection will suppress these transient voltage
peaks. Each flash device should have a 0.1 μF ceramic capacitor connected between each V
CC
and
GND, and between its V
PP
and GND. These high-frequency, inherently low-inductance capacitors
should be placed as close as possible to the package leads.
相關(guān)PDF資料
PDF描述
TE28F640B3TC100 3 Volt Advanced Boot Block Flash Memory
TE28F320B3TC70 3 Volt Advanced Boot Block Flash Memory
TE28F640B3TC90 3 Volt Advanced Boot Block Flash Memory
TE28F320B3TC90 3 Volt Advanced Boot Block Flash Memory
TE28F004SC-100 BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TE28F004B5B80 制造商:Intel 功能描述:
TE28F004BEB120 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
TE28F004BET120 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
TE28F004BVB80 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
TE28F004BVT80 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
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