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參數(shù)資料
| 型號： | T7688 |
| 廠商： | Lineage Power |
| 英文描述： | 5.0 V E1/CEPT Quad Line Interface(5.0 V E1/CEPT四線接口) |
| 中文描述： | 5.0V的E1/CEPT四線接口（5.0V的E1/CEPT四線接口） |
| 文件頁數(shù)： | 24/38頁 |
| 文件大小： | 577K |
| 代理商： | T7688 |
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Data Sheet
May 1998
T7688 5.0 V E1/CEPT Quad Line Interface
24
Lucent Technologies Inc.
Microprocessor Interface
(continued)
Microprocessor Interface Register Architecture
(continued)
Global Control Register Overview (0100, 0101)
The bits in the global control registers in Table 14 and Table 15 allow the microprocessor to configure the various
device functions over all the four channels. All the control bits (with the exception of LOSSTD and ICTMODE) are
active-high. These are read/write registers.
Table 14. Global Control Register (0100)
Bits
Symbol
Description
Global Control Register (4)
The GMASK bit globally masks all the channel alarms when GMASK = 1, pre-
venting all the receiver and transmitter alarms from generating an interrupt.
GMASK = 1 after a device reset.
The SWRESET provides the same function as the hardware reset. It is used
for device initialization through the microprocessor interface. The software
reset bit does not have a powerup default state, therefore, the first write to the
device must clear this bit.
The LOSSTD bit must be written to 0.
The ICTMODE bit changes the function of the ICT pin. ICTMODE = 0 after a
device reset.
A HIGHZ bit is available for each individual channel. When HIGHZ = 1, the
TTIP and TRING transmit drivers for the specified channel are placed in a
high-impedance state. HIGHZ[1:4] = 1 after a device reset.
0
GMASK
1
SWRESET
2
3
LOSSTD
ICTMODE
4—7
HIGHZ[1:4]
Table 15. Global Control Register (0101)
Bits
Symbol
Description
Global Control Register (5)
The CDR bit is used to enable and disable the clock/data recovery function.
The JAR is used to enable and disable the jitter attenuator function in the
receive path. The JAR and JAT control bits are mutually exclusive; i.e., either
JAR or the JAT control bit can be set, but not both.
The JAT is used to enable and disable the jitter attenuator function in the trans-
mit path. The JAT and JAR control bits are mutually exclusive; i.e., either JAT or
the JAR control bit should be set, but not both.
The CODE bit is used to enable and disable the HDB3 zero substitution coding
(decoding) in the transmit (receive) path. It is used in conjunction with the
DUAL bit and is valid only for single-rail operation.
The DUAL bit is used to select single- or dual-rail mode of operation.
The ALM bit selects the transmit and receive data polarity (i.e., active-low or
active-high). The ALM and ACM bits are used together to determine the trans-
mit and receive data retiming modes.
The ACM bit selects the positive or negative edge of the receive clock
(RCLK[1:4]) for receive data retiming. The ACM and ALM bits are used together
to determine the transmit and receive data retiming modes.
The LOSSD bit selects the shutdown function for the digital loss of signal alarm
(DLOS).
0
1
CDR
JAR
2
JAT
3
CODE
4
5
DUAL
ALM
6
ACM
7
LOSSD
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