參數(shù)資料
型號(hào)： T7688
廠商： Lineage Power
英文描述： 5.0 V E1/CEPT Quad Line Interface(5.0 V E1/CEPT四線接口)
中文描述： 5.0V的E1/CEPT四線接口（5.0V的E1/CEPT四線接口）
文件頁(yè)數(shù)： 21/38頁(yè)
文件大小： 577K
代理商： T7688
Data Sheet
May 1998
T7688 5.0 V E1/CEPT Quad Line Interface
21
Lucent Technologies Inc.
Microprocessor Interface
(continued)
Microprocessor Clock (MPCLK) Specifications
The microprocessor interface is designed to operate at clock speeds up to 16.384 MHz without requiring any wait-
states. Wait-states may be needed if higher microprocessor clock speeds are required. The microprocessor clock
(MPCLK, pin 83) specification is shown in Table 10. This clock must be supplied only if the RDY_DTACK and INT
outputs are required to be synchronous to MPCLK. Otherwise, the MPCLK pin must be connected to ground
(GND
D
).
Internal Chip Select Function
When the microprocessor interface is configured to operate in the multiplexed address/data bus modes (MPUX =
1), the user has access to an internal chip select function. This function allows a microprocessor to selectively read
or write a specific quad line interface device in a system of up to eight devices on the microprocessor bus. Exter-
nally tying CS = 0 (pin 24) and A3 = 1 (pin 79) on every line interface device enables the internal chip select func-
tion. Individual device addresses are established by externally connecting the other three address pins A[2:0] to a
unique address value in the range of 000 through 111. In order for a line interface device to respond to the register
read or write request from the microprocessor, the address data bus AD[6:4] (pins 70, 71, 72) must match the spe-
cific address defined on A[2:0]. If
CS
and A3 pins are tied low, the internal chip select function is disabled and all
line interface devices will respond to a microprocessor write request. However, if
CS
= 1, none of the line interface
devices will respond to the microprocessor read/write request.
Microprocessor Interface Register Architecture
The register bank architecture of the microprocessor interface is shown in Table 11. The register bank consists of
sixteen 8-bit registers classified as alarm registers, global control registers, and channel configuration/mainte-
nance registers. Registers 0 and 1 are the alarm registers used for storing the various device alarm status and are
read-only. All other registers are read/write. Registers 2 and 3 contain the individual mask bits for the alarms in reg-
isters 0 and 1. Registers 4 and 5 are designated as the global control registers used to set up the functions for all
four channels. The channel configuration registers in registers 6 through 9 are used to configure the individual
channel functions and parameters. Registers 10 and 11 must be cleared by the user after a powerup for proper
device operation. Registers 12 through 15 are reserved for proprietary functions and must not be addressed during
operation. The following sections describe these registers in detail.
Table 10. Microprocessor Input Clock Specifications
Name
Symbol
Period and
Tolerance
T
rise
Typ
T
fall
Typ
Duty Cycle
Unit
Min High
Min Low
MPCLK
t1
61 to 323
5
5
27
27
ns
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