參數(shù)資料
型號(hào)： T7688
廠商： Lineage Power
英文描述： 5.0 V E1/CEPT Quad Line Interface(5.0 V E1/CEPT四線(xiàn)接口)
中文描述： 5.0V的E1/CEPT四線(xiàn)接口（5.0V的E1/CEPT四線(xiàn)接口）
文件頁(yè)數(shù)： 2/38頁(yè)
文件大?。?/td> 577K
代理商： T7688
2
Table of Contents
Contents
Page
Contents
Page
Lucent Technologies Inc.
Data Sheet
May 1998
T7688 5.0 V E1/CEPT Quad Line Interface
Features .................................................................... 1
Applications ............................................................... 1
Description ................................................................. 1
Block Diagram ........................................................... 3
Pin Information .......................................................... 4
System Interface Pin Options ................................ 9
Receiver .................................................................. 10
Data Recovery ..................................................... 10
Jitter ..................................................................... 10
Receiver Configuration Modes ............................ 10
Clock/Data Recovery Mode (CDR) ................... 10
Zero Substitution Decoding (CODE) ................. 10
Alternate Logic Mode (ALM) ............................. 10
Alternate Clock Mode (ACM) ............................ 11
Loss Shut Down (LOSSD) ................................ 11
Receiver Alarms .................................................. 11
Analog Loss of Signal (ALOS) Alarm ................ 11
Digital Loss of Signal (DLOS) Alarm ................. 11
Bipolar Violation (BPV) Alarm ........................... 11
CEPT Receiver Specifications ............................. 12
Transmitter .............................................................. 13
Output Pulse Generation ..................................... 13
Jitter ..................................................................... 13
Transmitter Configuration Modes ........................ 14
Zero Substitution
Encoding/Decoding (CODE) ........................... 14
All Ones (AIS, Blue Signal) Generator (TBS) ... 14
Transmitter Alarms .............................................. 14
Loss of Transmit Clock (LOTC) Alarm .............. 14
Transmit Driver Monitor (TDM) Alarm ............... 14
CEPT Transmitter Pulse ...................................... 15
Template and Specifications ............................. 15
Jitter Attenuator ....................................................... 16
Data Delay ........................................................... 16
Generated (Intrinsic) Jitter ................................... 16
Jitter Transfer Function ........................................ 16
Jitter Tolerance .................................................... 16
Jitter Attenuator Enable ....................................... 16
Jitter Attenuator Receive Path Enable (JAR) .... 17
Jitter Attenuator Transmit Path Enable (JAT) ... 17
Loopbacks ...............................................................17
Full Local Loopback (FLLOOP) ...........................17
Remote Loopback (RLOOP) ................................17
Digital Local Loopback (DLLOOP) .......................17
Other Features ........................................................18
Powerdown (PWRDN) .........................................18
RESET (
RESET
, SWRESET) ...............................18
Loss of XCLK Reference Clock (LOXC) ..............18
In-Circuit Testing and Driver 3-State (ICT) ..........18
Microprocessor Interface .........................................19
Overview ..............................................................19
Microprocessor Configuration Modes ..................19
Microprocessor Interface Pinout Definitions ........20
Microprocessor Clock (MPCLK) Specifications ...21
Internal Chip Select Function ...............................21
Microprocessor Interface Register Architecture ...21
Alarm Register Overview (0000, 0001) .............23
Alarm Mask Register Overview (0010, 0011) ...23
Global Control Register
Overview (0100, 0101) ...................................24
Channel Configuration Register
Overview (0110—1001) ..................................25
Other Registers .................................................25
I/O Timing ............................................................26
XCLK Reference Clock ............................................31
Power Supply Bypassing .........................................31
External Line Interface Circuitry ...............................32
Absolute Maximum Ratings .....................................33
Handling Precautions ..............................................33
Operating Conditions ...............................................33
Timing Characteristics .............................................34
Outline Diagram .......................................................36
100-Pin BQFP ......................................................36
Ordering Information ................................................37
DS98-231TIC Replaces DS96-172TIC to Incorporate
the Following Updates..............................................37
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