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2-8
SYM53C875/875E Data Manual
Functional Description
Parity Options
extra parity checking is always enabled for the
SYM53C875N. T he host system must support
these pins. T his feature is not register selectable. A
parity error on any Byte Parity pin for PCI master
read or slave write operations will cause a fatal
DMA interrupt; SCRIPT S will stop running. T his
interrupt can be masked with the EBPE Interrupt
Enable bit, bit 1 in the DIEN register. T hese addi-
tional parity pins in no way affect the generation or
checking of the PCI specified parity line.
Table 2-2: Bits Used for Parity Control and Generation
BIt Name
Assert SAT N/ on
Parity Errors
Enable Parity
Checking
Location
SCNT L0, Bit 1
Description
Causes the SYM53C875 to automatically assert SAT N/ when it
detects a parity error while operating as an initiator.
Enables the SYM53C875 to check for parity errors. T he
SYM53C875 checks for odd parity. T his bit also checks for par-
ity errors on the four additional parity pins on the
SYM53C875N.
Determines the SCSI parity sense generated by the
SYM53C875 to the SCSI bus.
Causes the SYM53C875 not to halt operations when a parity
error is detected in target mode.
SCNT L0, Bit 3
Assert Even SCSI
Parity
Disable Halt on
SAT N/ or a Parity
Error (Target Mode
Only)
Enable Parity Error
Interrupt
Parity Error
SCNT L1, Bit 2
SCNT L1, Bit 5
SIEN0, Bit 0
Determines whether the SYM53C875 will generate an interrupt
when it detects a SCSI parity error.
T his status bit is set whenever the SYM53C875 has detected a
parity error on the SCSI bus.
T his status bit represents the active high current state of the
SCSI SDP0 parity signal.
T his bit represents the active high current state of the SCSI
SDP1 parity signal.
T hese bits reflect the SCSI odd parity signal corresponding to
the data latched into the SIDL register.
Enables parity checking during master data phases.
SIST 0, Bit 0
Status of SCSI
Parity Signal
SCSI SDP1 Signal
SSTAT 0, Bit 0
SSTAT 2, Bit 0
Latched SCSI Parity
SSTAT 2, Bit 3 and
SSTAT 1, Bit 3
CT EST 4, Bit 3
Master Parity Error
Enable
Master Data Parity
Error
Master Data Parity
Error Interrupt
Enable
Extended Byte Par-
ity Error Interrupt
Enable
(SYM53C875N
only)
DSTAT, Bit 6
Set when the SYM53C875 as a master detects that a target
device has signalled a parity error during a data phase.
By clearing this bit, a Master Data Parity Error will not cause
IRQ/ to be asserted, but the status bit will be set in the DSTAT
register.
By clearing this bit, an Extended Byte Parity Error will not cause
IRQ/ to be asserted, but the status bit will be set in the DSTAT
register.
DIEN, Bit 6
DIEN, Bit 1