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參數(shù)資料
| 型號(hào)： | SYM53C875E |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O 處理器) |
| 中文描述： | 的PCI -超的SCSI I / O處理器（個(gè)PCI -超的SCSI的I / O處理器） |
| 文件頁(yè)數(shù)： | 139/243頁(yè) |
| 文件大?。?/td> | 1362K |
| 代理商： | SYM53C875E |
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SCSI Operating Registers
SYM53C875/875E Data Manual
5-53
Register 4F (CF)
SCSI Test T hree (ST EST 3)
Read/Write
Bit 7
T E (TolerANT E nable)
Setting this bit enables the active negation por-
tion of Symbios TolerANT technology. Active
negation causes the SCSI Request, Acknowl-
edge, Data, and Parity signals to be actively
deasserted, instead of relying on external pull-
ups, when the SYM53C875 is driving these
signals. Active deassertion of these signals will
occur only when the SYM53C875 is in an
information transfer phase. When operating in
a differential environment or at fast SCSI tim-
ings, TolerANT Active negation should be
enabled to improve setup and deassertion
times. Active negation is disabled after reset or
when this bit is cleared. For more information
on Symbios TolerANT technology, refer to
Chapter 1.
Note: T his bit must be set if the Enable Fast 20
bit in SCNT L3 is set.
Bit 6
ST R (SCSI FIFO Test Read)
Setting this bit places the SCSI core into a test
mode in which the SCSI FIFO can be easily
read. Reading the least significant byte of the
SODL register will cause the FIFO to unload.
T he functions are summarized in the table
below.
Bit 5
HSC (Halt SCSI Clock)
Asserting this bit causes the internal divided
SCSI clock to come to a stop in a glitchless
manner. T his bit may be used for test purposes
or to lower I
DD
during a power down mode.
T his bit is used when the SCSI clock doubler is
operating. For additional information on the
clock doubler, please see Chapter 2.
Bit 4
DSI (Disable Single Initiator
Response)
If this bit is set, the SYM53C875 will ignore all
bus-initiated selection attempts that employ
the single-initiator option from SCSI-1. In
order to select the SYM53C875 while this bit
is set, the SYM53C875’s SCSI ID and the ini-
tiator’s SCSI ID must both be asserted. T his
bit should be asserted in SCSI-2 systems so
that a single bit error on the SCSI bus will not
be interpreted as a single initiator response.
Bit 3 S16 (16-bit System)
If this bit is set, all devices in the SCSI system
implementation are assumed to be 16 bits. T his
causes the SYM53C875 to always check the
parity bit for SCSI IDs 15-8 during bus-initi-
ated selection or reselection, assuming parity
checking has been enabled. If an 8-bit SCSI
device attempts to select the SYM53C875
while this bit is set, the SYM53C875 will
ignore the selection attempt, because the parity
bit for IDs 15-8 will be undriven. See the
description of the Enable Parity Checking bit
in the SCNT L0 register for more information.
Bit 2
T T M (T imer Test Mode)
Asserting this bit facilitates testing of the selec-
tion time-out, general purpose, and hand-
shake-to-handshake timers by greatly reducing
all three time-out periods. Setting this bit starts
all three timers and if the respective bits in the
SIEN1 register are asserted, the SYM53C875
will generate interrupts at time-out. T his bit is
intended for internal manufacturing diagnosis
and should not be used.
TE
7
STR
6
HSC
5
DSI
4
S16
3
TTM
2
CSF
1
STW
0
Default>>>
0
0
0
0
0
0
0
0
Register
Name
Register
Operation
FIFO Bits
FIFO
Function
SODL
SODL0
SODL1
Read
Read
Read
15-0
7-0
15-8
Unload
Unload
None
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相關(guān)代理商/技術(shù)參數(shù) |
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