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| 型號： | SYM53C875E |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O 處理器) |
| 中文描述： | 的PCI -超的SCSI I / O處理器（個(gè)PCI -超的SCSI的I / O處理器） |
| 文件頁數(shù)： | 29/243頁 |
| 文件大小： | 1362K |
| 代理商： | SYM53C875E |
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Functional Description
Loopback Mode
SYM53C875/875E Data Manual
2-7
When a dword is accessed, no repositioning of the
individual bytes is necessary since dwords are
addressed by the address of the least significant
byte. SCRIPT S always uses dwords in 32-bit sys-
tems, so compatibility is maintained between sys-
tems using different byte orientations. When less
than a dword is accessed, individual bytes must be
repositioned. Internally, the SYM53C875 adjusts
the byte control logic of the DMA FIFO and regis-
ter decodes to access the appropriate byte lanes.
T he registers will always appear on the same byte
lane, but the address of the register will be reposi-
tioned.
Big/Little Endian mode selection has the most
effect on individual byte access. Internally, the
SYM53C875 adjusts the byte control logic of the
DMA FIFO and register decodes to enable the
appropriate byte lane. T he registers will always
appear on the same byte lane, but the address of
the register will be repositioned.
Data to be transferred between system memory
and the SCSI bus always starts at address zero and
continues through address ‘n’ - there is no byte
ordering in the chip. T he first byte in from the
SCSI bus goes to address 0, the second to address
1, etc. Going out onto the SCSI bus, address zero
is the first byte out on the SCSI bus, address 1 is
the second byte, etc. T he only difference is that in
a Little Endian system, address 0 will be on byte
lane 0, and in Big Endian mode address zero will
be on byte lane 3.
Correct SCRIPT S will be generated if the
SCRIPT S compiler is run on a system that has the
same byte ordering as the target system. Any
SCRIPT S patching in memory must patch the
instruction with the byte ordering that the
SCRIPT S processor expects.
Software drivers for the SYM53C875 should
access registers by their logical name (i.e.,
SCNT L0) rather than by their address. T he logical
name should be equated to the register’s Big
Endian address in Big Endian mode (SCNT L0 =
03h), and its Little Endian address in Little
Endian Mode (SCNT L0 = 00h). T his way, there is
no change to the software when moving from one
mode to the other; only the equate statement set-
ting the operating modes needs to be changed.
Addressing of registers from within a SCRIPT S
instruction is independent of bus mode. Internally,
the SYM53C875 always operates in Little Endian
mode.
Loopback Mode
T he SYM53C875 loopback mode allows testing of
both initiator and target functions and, in effect,
lets the chip communicate with itself. When the
Loopback Enable bit is set in the ST EST 1 register,
the SYM53C875 allows control of all SCSI sig-
nals, whether the SYM53C875 is operating in ini-
tiator or target mode. For more information on
this mode of operation, refer to the
Symbios Logic
PCI-SCSI Programming Guide
.
Parity Options
T he SYM53C875 implements a flexible parity
scheme that allows control of the parity sense,
allows parity checking to be turned on or off, and
has the ability to deliberately send a byte with bad
parity over the SCSI bus to test parity error recov-
ery procedures. Table 2-2 defines the bits that are
involved in parity control and observation. Table 2-
3 describes the parity control function of the
Enable Parity Checking and Assert SCSI Even
Parity bits in the SCNT L0 register. Table 2-4
describes the options available when a parity error
occurs.
T he SYM53C875N has four additional parity pins
for checking incoming data on the PCI bus. T hese
pins are assigned to each byte of the PCI address/
data bus, and work in addition to the PAR (PCI
parity) pin. In PCI master read or slave write oper-
ations, each byte of incoming data on the PCI bus
is checked against its corresponding parity line, in
addition to the normal parity checking against the
PCI PAR signal. In PCI master write or slave read
operations, parity is generated for each byte. T his
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