參數(shù)資料
型號(hào)： SYM53C825A
廠商： LSI Corporation
英文描述： PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器)
中文描述： 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器）
文件頁(yè)數(shù)： 48/225頁(yè)
文件大?。?/td> 1237K
代理商： SYM53C825A
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PCI Functional Description
PCI Cache Mode
3-4
SYM53C825A/53C825AE Data Manual
Memory Move
Misalignment
T he SYM53C825A will not operate in a cache
alignment mode when a Memory Move instruc-
tion type is issued and the read and write addresses
are different distances from the nearest cache line
boundary. For example, if the read address is
0x21F and the write address is 0x42F, and the
cache line size is eight (8), the addresses are byte
aligned, but they are not the same distance from
the nearest cache boundary. T he read address is 1
byte from the cache boundary 0x220 and the write
address is 17 bytes from the cache boundary
0x440. In this situation, the chip will not align to
cache boundaries and will operate as an
SYM53C825.
Memory Write
and Invalidate Command
T he Memory Write and Invalidate command is
identical to the Memory Write command, except
that it additionally guarantees a minimum transfer
of one complete cache line; i.e., the master intends
to write all bytes within the addressed cache line in
a single PCI transaction unless interrupted by the
target. T his command requires implementation of
the PCI Cache Line Size register at address 0Ch in
PCI configuration space. T he SYM53C825A
enables Memory Write and Invalidate cycles when
bit 0 in the CT EST 3 register (WRIE) and bit 4 in
the PCI Command register are set. T his will cause
Memory Write and Invalidate commands to be
issued when the following conditions are met:
1. T he CLSE bit, WRIE bit, and PCI
configuration Command register, bit 4 must be
set.
2. T he cache line size register must contain a
legal burst size (2, 4, 8, 16, 32, 64, or 128)
value AND that value must be less than or
equal to the DMODE burst size.
3. T he chip must have enough bytes in the DMA
FIFO to complete at least one full cache line
burst.
4. T he chip must be aligned to a cache line
boundary.
When these conditions have been met, the
SYM53C825A will issue a Write and Invalidate
command instead of a Memory Write command
during all PCI write cycles.
Multiple Cache Line Transfers
T he Write and Invalidate command can write mul-
tiple cache lines of data in a single bus ownership.
T he chip issues a burst transfer as soon as it
reaches a cache line boundary. T he size of the
transfer will not automatically be the cache line
size, but rather a multiple of the cache line size as
allowed for in the Revision 2.1 of the PCI specifi-
cation. T he logic will select the largest multiple of
the cache line size based on the amount of data to
transfer, with the maximum allowable burst size
being that determined from the DMODE Burst
Size bits and CT EST 5, bit 2. If multiple cache
line size transfers are not desired, the DMODE
burst size can be set to exactly the cache line size
and the chip will only issue single cache line trans-
fers.
After each data transfer, the chip re-evaluates the
burst size based on the amount of remaining data
to transfer and again selects the highest possible
multiple of the cache line size, no larger than the
DMODE burst size. T he most likely scenario of
this scheme is that the chip will select the
DMODE burst size after alignment, and issue
bursts of this size. T he burst size will, in effect,
throttle down toward the end of a long Memory
Move or Block Move transfer until only the cache
line size burst size is left; the chip will finish the
transfer with this burst size.
Latency
In accordance with the PCI specification, the
chip's latency timer will be ignored when issuing a
Write and Invalidate command such that when a
latency time-out has occurred, the SYM53C825A
will continue to transfer up until a cache line
boundary. At that point, the chip will relinquish
the bus, and finish the transfer at a later time using
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