參數(shù)資料
型號(hào)： ST92R195C
英文描述： ROMLESS HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
中文描述： 無(wú)ROM HCMOS微控制器屏幕顯示和圖文電視數(shù)據(jù)限幅器
文件頁(yè)數(shù)： 86/208頁(yè)
文件大?。?/td> 2312K
代理商： ST92R195C
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ST92R195C - TELETEXT DISPLAY STORAGE RAM INTERFACE
TDSRAM
(Cont’d)
8.3.2 Functional Description
The Teletext Data Storage RAM Interface (TRI)
manages the data flows between the different sub-
units (display, acquisition, 40-byte buffer, CPU in-
terface) and the internal RAM. A specific set of
buses (8 bit data TRIDbus, 13 bit address TRIA-
bus) is dedicated to these data flows.
As this TDSRAM interface has to manage TV ori-
ented real time signals (On-Screen-Display, Tele-
text slicing storage):
– Its timing generator uses the same frequency
generator as for the Display (Pixel frequency
multiplier),
– Its controller is hardware synchronized to the ba-
sic horizontal and vertical sync signals got
through the CSYNC Controller,
– Its architecture gives priority to the TV real time
constraints: whenever there is any access con-
tention between the CPU (only in case of direct
CPU access) and one of the hardware units, the
CPU automatically enters a "wait" configuration
until its request is serviced.
8.3.2.1 TV Line Timesharing
During a TV line, to maintain maximum perform-
ance, a continuous cycle is run repetitively. This
cycle is divided in 8 sub-cycles called "slots".
This 8-slot cycle is repeated continuously until the
next TV line-start occurs (horizontal sync pulse de-
tected). When a horizontal sync pulse is detected,
the running slot is completed and the current cycle
is broken.
The following naming convention is used: "ACQ"
stands for Acquisition storage slot, "CPU" stands
for direct CPU access slot, "DIS" stands for Dis-
play reading slot, "MBT" stands for multi-byte
transfer. Each slot represents a single byte ex-
change (read or write) between the TDSRAM
memory and the other units:
Acquisition Storage (ACQ).
1 byte issued from
the Teletext Acquisition unit written to the TD-
SRAM, the address is defined by the acquisition
address generator.
Display Reading (DIS).
1 byte is read from the
TDSRAM and sent to the display unit, the address
being defined by the display address generator.
Multi-Byte Transfer (MBT).
1 byte of the 40 bytes
Buffer is exchanged (read or written) between the
40-byte Buffer and the TDSRAM, the address be-
ing defined by the 40-byte buffer address genera-
tor.
CPU Access (CPU).
1 byte is exchanged (read or
written) between the TDSRAM and the CPU, the
address being defined by the CPU address bus.
8.3.2.2 TV Field Timesharing
The choice between Acquisition and Display cy-
cles is done automatically on a TV line basis.
The complete TV field start (VBI) is affected to Ac-
quisition cycles up to end of line 24. The rest of the
TV field is affected to Display cycles up to the next
field (next vertical sync pulse).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST92T141K4B6 功能描述:8位微控制器 -MCU OTP EPROM 16K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST92T141K4M6 功能描述:8位微控制器 -MCU OTP EPROM 16K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST92T163R4T1 功能描述:8位微控制器 -MCU OTP EPROM 20K USB/I2 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST92T196/JAP 制造商:STMicroelectronics 功能描述:
ST92T96N9B1/AIN 制造商:STMicroelectronics 功能描述:
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