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ST92R195C - INTERRUPTS
3.6 EXTERNAL INTERRUPTS
The standard ST9 core contains 8 external inter-
rupts sources grouped into four pairs.
Table 6. External Interrupt Channel Grouping
Each source has a trigger control bit TEA0,..TED1
(R242,EITR.0,..,7 Page 0) to select triggering on
the rising or falling edge of the external pin. If the
Trigger control bit is set to “1”, the corresponding
pending bit IPA0,..,IPD1 (R243,EIPR.0,..,7 Page
0) is set on the input pin rising edge, if it is cleared,
the pending bit is set on the falling edge of the in-
put pin. Each source can be individually masked
through
the
corresponding
IMA0,..,IMD1 (EIMR.7,..,0). See
Figure 24
.
The priority level of the external interrupt sources
can be programmed among the eight priority lev-
els with the control register EIPLR (R245). The pri-
ority level of each pair is software defined using
the bits PRL2, PRL1. For each pair, the even
channel (A0,B0,C0,D0) of the group has the even
priority level and the odd channel (A1,B1,C1,D1)
has the odd (lower) priority level.
control
bit
Figure 23. Priority Level Examples
n
Figure 23
shows an example of priority levels.
Figure 24
gives an overview of the External inter-
rupt control bits and vectors.
– The source of the interrupt channel INTA0 can
be selected between the external pin INT0 (when
IA0S = “1”, the reset value) or the On-chip Timer/
Watchdog peripheral (when IA0S = “0”).
– INTA1: by selecting INTS equal to 0, the stand-
ard Timer0 is chosen as the interrupt.
– The source of the interrupt channel INTB0 can
be selected between the external pin INT2 (when
(SPEN,BMS)=(0,0)) or the SPI peripheral.
– INTB1: setting AD-INT.0 to 1 selects the ADC as
the interrupt source for channel INTB1.
– Setting bit 2 of the CSYCT to 1 selects EOFVBI
interrupt as the source for INTC0. Setting this bit
to 0 selects external interrupt on INT4.
– Setting FSTEN (bit 3 of the CSYCT register) to 1
selects FLDST interrupt for channel INTC1. Set-
ting this bit to 0 selects external interrupt INT5.
– INTD0: by selecting INTS equal to 0, the stand-
ard Timer1 is chosen as the interrupt.
Interrupt channels INTD0 and INTD1 have an in-
put pin as source. However, the input line may be
multiplexed with an on-chip peripheral I/O or con-
nected to an input pin that performs also another
function.
Warning:
When using channels shared by both
external interrupts and peripherals, special care
must be taken to configure their control registers
for both peripherals and interrupts.
Table 7. Internal/External Interrupt Source
External Interrupt
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
Channel
INTD1
INTD0
INTC1
INTC0
INTB1
INTB0
INTA1
INTA0
1
0
0
1
0
0
1
PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A
INT.D1:
INT.C1: 001=1
INT.D0:
SOURCE
PRIORITY
PRIORITY
SOURCE
INT.A0: 010=2
INT.A1: 011=3
INT.B1: 101=5
INT.B0: 100=4
INT.C0: 000=0
EIPLR
VR000151
0
100=4
101=5
Channel
Internal Interrupt
Source
Timer/Watchdog
Standard Timer0
SPI Interrupt
A/D Converter
EOFVBI
(SYNC inter)
FLDST
(SYNC inter)
Standard Timer1
none
External Interrupt
Source
INT0
INT1
INT2
INT3
INTA0
INTA1
INTB0
INTB1
INTC0
INT4
INTC1
INT5
INTD0
INTD1
INT6
INT7