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參數(shù)資料
| 型號(hào)： | SI3012-KS |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 8/64頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE-SIDE DAA 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 系列： | ISOcap™ |
| 數(shù)據(jù)格式： | V.90 |
| 電源電壓： | 3.3 V ~ 5 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC N |
| 包裝： | 管件 |
Si3038
16
Re
v.
2.01
Ty
pical
Application
Circuit
C2
R30
SDATA_IN
C20
Z4
R11
FB1
R12
C32
R28
+
C5
U2
Si3012/4
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
TSTA/QE2
TSTB/DCT
IGND
C1B
RNG1
RNG2
QB
QE
VREG
NC/VREG2
NC/REF
DCT/REXT2
REXT
RX
NC/FILT
TX/FILT2
See Note 5
R24
R23
RV2
Q2
R8
C31
FB2
R2
BITCLK
C29
R16
Note 1: This design targets two basic builds:
- An FCC and JATE compliant design using the
Si3036 chipset.
- A worldwide design using the Si3038 chipset.
Note 2: R12, R13 and C14 are only required if
complex AC termination is used (ACT bit = 1).
Note 3: See "Billing Tone Detection" section for
optional billing tone filter (Germany, Switzerland,
South Africa).
Note 4: See Appendix A for applications requiring
UL 1950 3rd edition compliance.
Note 5: For Si3036 designs R29 is populated with
a 0 ohm resistor and R30 is not installed. For
Si3038 designs R29 is not installed and R30 is
populated with a 0 ohm resistor.
Note 6: Refer to Appendix B for information
regarding L1 and L2.
See Note 6
ID1#
SDATA_OUT
R18
C11
Q1
No Ground Plane In DAA Section
D3
BAV99
C16
C18
L2
R5
Q3
RESET#
R19
R15
J1
RJ-11
1
2
3
4
5
6
R27
R9
+ C23
R7
RV1
R17
Z1
C35
+
C14
C9
C34
R4
+3.3VD
C8
C22
L1
R1
C6
C10
D2
AOUT
R13
U1
Si3024
2
1
3
4
5
6
7
89
10
11
12
13
14
15
16
XOUT
MCLK/XIN
BIT_CLK
VD
SDATA_IN
SDATA_OUT
SYNC
RESET
AOUT
ID0
C1A
GND
VA
ID1
GPIO_B
GPIO_A
R29
R21
C3
D1
R6
SYNC
C1
Z5
C4
C30
C28
Y1
24.576 MHz
Q4
C24
ID0#
+
C12
R10
D4
BAV99
C25
C13
C19
R22
C7
Figure 19. Typical Applications Circuit for the Dual Design Si3036 and Si3038
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