參數(shù)資料
型號(hào)： SI3012-KS
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 17/64頁(yè)
文件大小： 0K
描述： IC LINE-SIDE DAA 16SOIC
標(biāo)準(zhǔn)包裝： 48
系列： ISOcap™
數(shù)據(jù)格式： V.90
電源電壓： 3.3 V ~ 5 V
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC N
包裝： 管件
Si3038
24
Rev. 2.01
Figure 23. CTR21 Mode I/V Characteristics
DC Termination Considerations
Under certain line conditions, it may be beneficial to use
other dc termination modes not intended for a particular
world region. For instance, in countries that comply with
the CTR21 standard, improved distortion characteristics
can be seen for very low loop current lines by switching
to FCC mode. Thus, after going off-hook in CTR21
mode, the loop current monitor bits (LCS[3:0]) may be
used to measure the loop current, and if LCS[3:0] < 3, it
is recommended that FCC mode be used.
Additionally, for very low voltage countries, such as
Japan and Malaysia, the following procedure may be
used to optimize distortion characteristics and maximize
transmit levels:
1. When first going off-hook, use the Japan mode with the
VOL bits (Register 62h, bits 6:5) set to 01.
2. Measure the loop current using the LCS[3:0] bits.
3. If LCS[3:0]
≤ 2, maintain the current settings and proceed
with normal operation.
4. If LCS[3:0]
≥ 3, switch to FCC mode, set the VOL bit to 0,
and proceed with normal operation.
Note: A single decision of dc termination mode following off-
hook is appropriate for most applications. However,
during PTT testing, a false dc termination I/V curve
may be generated if the dc I/V curve is determined fol-
lowing a single off-hook event.
Finally,
Australia
has
separate
dc
termination
requirements for line seizure versus line hold. Japan
mode may be used to satisfy both requirements.
However, if a higher transmit level for modem operation
is desired, switch to FCC mode 500 ms after the initial
off-hook. This will satisfy the Australian dc termination
requirements.
AC Termination
The Si3038 has two ac termination impedances,
selected with the ACT bit in register 5Ch.
ACT=0 is a real, nominal 600
termination which
satisfies the impedance requirements of FCC part 68,
JATE, and other countries. This real impedance is set
by circuitry internal to the Si3038 as well as the resistor
R2 connected to the REXT pin.
ACT=1 is a complex impedance which satisfies the
impedance requirements of Australia, New Zealand,
South Africa, CTR21, and some European NET4
countries such as the UK and Germany. This complex
impedance is set by circuitry internal to the Si3038 as
well as the complex network formed by R12, R13, and
C14 connected to the REXT2 pin.
Ring Detection
The ring signal is capacitively coupled from TIP and
RING to the RNG1 and RNG2 pins. The Si3038
supports either full- or half-wave ring detection. With
full-wave ring detection, the designer can detect a
polarity reversal as well as the ring signal. See "Caller
ID" on page 28. The ring detection threshold is
programmable with the RT bit in register 5Ch.
The ring detector output can be monitored in one of
three ways. The first method uses the GPIO1(GPIO11)
bit of Slot12. The second method uses the register bits
RDTP and RDTN in register 5Eh. The final method uses
the SDATA_IN output.
The AC’97 controller must detect the frequency of the
ring signal in order to distinguish a ring from pulse
dialing by telephone equipment connected in parallel.
The ring detector mode is controlled by the RFWE bit of
register 5Ch. When the RFWE is 0 (default mode), the
ring detector operates in half-wave rectifier mode. In
this mode, only positive ringing signals are detected. A
positive ringing signal is defined as a voltage greater
than the ring threshold across RNG1-RNG2. RNG1 and
RNG2 are pins 5 and 6 of the Si3014. Conversely, a
negative ringing signal is defined as a voltage less than
the negative ring threshold across RNG1-RNG2.
When the RFWE is 1, the ring detector operates in full-
wave rectifier mode. In this mode, both positive and
negative ring signals are detected.
When RFWE is 0, the GPIO1(GPIO11) bit will be set for
a period of time. The GPIO1(GPIO11) bit will not be set
for a negative ringing signal. The GPIO1(GPIO11) bit
will act as a one shot. Whenever a new ring signal is
detected, the one shot is reset. If no new ring signals
are detected prior to the one shot counter counting
down to zero, then the GPIO1(GPIO11) bit will return to
45
40
35
30
25
20
15
10
5
.015 .02 .025 .03 .035 .04 .045 .05 .055 .06
Loop Current (A)
CTR21 DCT Mode
V
o
lta
ge
Ac
ro
ss
DA
A
(
V
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