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| 型號(hào)： | SI3012-KS |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 31/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE-SIDE DAA 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 系列： | ISOcap™ |
| 數(shù)據(jù)格式： | V.90 |
| 電源電壓： | 3.3 V ~ 5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC N |
| 包裝： | 管件 |
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Si3038
Rev. 2.01
37
AC-Link Low Power Mode
The AC-link signals can be placed in a low-power mode.
When AC’97’s Powerdown Register is programmed to
the appropriate value, both BIT_CLK and SDATA_IN will
be brought to, and held, at a logic low voltage level.
Figure 32. AC-Link Powerdown Timing
BIT_CLK
and
SDATA_IN
are
transitioned
low
immediately following the decode of the write to the
register 56h with MLNK. When the AC’97 controller
driver is at the point where it is ready to program the
AC-link into its low-power mode, slots 1 and 2 are
assumed to be the only valid stream in the audio output
frame.
The AC’97 controller should also drive SYNC and
SDATA_OUT low after programming the Si3038 to this
low-power mode.
When the Si3038 has been instructed to halt BIT_CLK,
a special wake up protocol must be used to bring the
AC-link to the active mode because normal audio output
and input frames cannot be communicated in the
absence of BIT_CLK.
Note: The Si3038’s PLL must be initialized before being
placed in sleep mode. PLL is initialized by writing a
sample rate in register 40h (42h).
Waking Up the AC-Link
There are two methods for bringing the AC-link out of a
low-power, halted mode. Regardless of the method, the
AC’97 controller performs the wake-up task.
AC-link protocol provides for a cold reset and a warm
reset. The current power down state ultimately dictates
which form of reset is appropriate. Unless a cold or
register reset (a write to the Reset register) is
performed, wherein the registers are initialized to their
default values, registers are required to keep state
during all power-down modes.
When powered down, reactivation of the AC-link
through reassertion of the SYNC signal must not occur
for a minimum of four audio frame times following the
frame in which the power down was triggered. When
AC-link powers up, the Si3038 indicates readiness
through the Codec Ready bit (input slot 0, bit 15).
The Si3038 can be enabled to indicate a power
management event has occurred (e.g., ring detection)
while in low-power mode. See "52h GPIO Pin Wake Up
Mask" on page 44 for more details.
Si3038 Cold Reset
A cold reset is achieved by asserting RESET for the
minimum specified time. By driving RESET low,
BIT_CLK and SDATA_OUT are activated, or re-
activated as the case may be, and all Si3038 control
registers are initialized to their default power on reset
values. It should be noted that while RESET is low, the
Si3038 will remain active. Upon the rising edge of
RESET the Si3038 will perform a cold reset. RESET is
an asynchronous Si3038 input.
Si3038 Warm Reset
A warm reset reactivates the AC-link without altering the
current Si3038 register values. A warm reset is signaled
by driving SYNC high for a minimum of 1 s in the
absence of BIT_CLK.
Within normal audio frames, SYNC is a synchronous
Si3038 input. However, in the absence of BIT_CLK,
SYNC is treated as an asynchronous input used in the
generation of a Warm reset to the Si3038.
The primary AC’97 codec will NOT respond with the
activation of BIT_CLK until SYNC has been sampled
low again by AC’97. This will preclude the false
detection of a new audio frame.
Table 25. Secondary Codec Register Access Slot 0 Bit Definitions
Output Tag Slot (16-bits)
Bit
Description
15
Frame Valid
14
Slot 1: Valid Command Address bit (Primary Codec only)
13
Slot 2: Valid Command Data bit (Primary Codec only)
12–3
Slot 3: 12 Valid bits as defined by AC’97
2
Reserved (Set to 0)
1–0
2-bit Codec ID field (00 reserved for Primary; 01, 10 indicate Secondary)
SYNC
SDATA_OUT
BIT_CLK
SDATA_IN
slot 12
prev. frame
TAG
Write to
56h
Data
MLNK
slot 12
prev. frame
TAG
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