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參數(shù)資料
| 型號： | SI3012-KS |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 29/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE-SIDE DAA 16SOIC |
| 標準包裝： | 48 |
| 系列： | ISOcap™ |
| 數(shù)據(jù)格式： | V.90 |
| 電源電壓： | 3.3 V ~ 5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC N |
| 包裝： | 管件 |
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Si3038
Rev. 2.01
35
Ready bit). Each new bit position is presented to AC-link
on a rising edge of BIT_CLK and subsequently sampled
by the AC’97 controller on the following falling edge of
BIT_CLK. This sequence ensures that data transitions
and subsequent sample points for both incoming and
outgoing data streams are time aligned.
SDATA_IN’s composite stream is MSB justified (MSB
first) with all non-valid bit positions (for assigned and
unassigned time slots) padded with 0s by the Si3024.
SDATA_IN data is sampled on the falling edges of
BIT_CLK by the AC’97 controller.
Slot 1: Status Address Port
The Status Address Port monitors status for Si3024
functions including, but not limited to, line-side
configuration.
Audio input frame slot 1’s stream echoes the control
register index for historical reference and for the data to
be returned in slot 2. (Assuming that slots 1 and 2 have
been tagged “valid” by the Si3024 during slot 0).
Status Address Port bit assignments:
Bit(19)—Reserved (padded with 0)
Bit(18:12)—Control Register Index (Echo of register
index for which data is being returned)
Bit(11:2)—SLOTREQ bits, bit 9 for Line 1 and bit 4
for Line 2. (See "Variable Sample Rate Signaling
Protocol" on page 32 for more details.)
Bit(1,0)—Reserved (padded with 0s)
The first bit (MSB) generated by the Si3024 is always
padded with a 0. The following seven bit positions
communicate the associated control register address
and the trailing 12 bit positions are padded with 0s by
the Si3024.
Slot 2: Status Data Port
The Status Data Port delivers 16-bit control register
read data.
Status Data Port bit assignments:
Bit(19:4)—Control Register Read Data (padded with
0s if tagged invalid by the Si3024)
Bit(3:0)—Reserved (padded with 0s)
If Slot 2 is tagged invalid by the Si3024, then the entire
slot is padded with 0s by the Si3024.
Slot 5: Modem Line 1 ADC
Audio input frame slot 5 contains MSB-justified modem
ADC output data for phone line #1 (ID = 0 or 1). The
modem ADC output resolution is 16 bits.
The Si3038 ships out its ADC output data MSB first and
pads any trailing non-valid bit positions with 0s to fill out
its 20-bit time slot.
Slot 5 data is sent by the controller at a rate below the
48 kHz rate of the AC-Link. Therefore, “tags” are used
to mark when there is valid data in slot 5. The tag for
slot 5 is bit 10 in slot 0.
The tag for slot 5 (and slot 10) is dependent on the
current power state. Slot 5 is inhibited by the following:
PRC/PRE bit is set (register 3E, bit 10/12); ADC is
powered down.
MLNK bit is set (register 56, bit 12); AC-Link halt is
impending.
Note that slot 5 is active when the DAA is on-hook in
order to pass ringer and caller-ID data.
Slot 10: Modem Line 2 ADC
Audio input frame for Line 2.
Slot 12: Modem GPIO Status
Slot 12 contains latency critical signals for the Si3014
and the GPIO of the Si3024. Slot 12 also reflects the
status of the link between the Si3024 and Si3014. See
Figure 31. AC-Link Audio Input Frame
Tag Phase
Data Phase
20.8 S
(48 KHz)
SYNC
SDATA_IN
BIT_CLK
Codec
Ready
slot(1)
slot(2)
"0"
19
0
19
0
19
0
19
0
slot(12)
End of previous
Audio Frame
Time Slot "Valid"
Bits
("1" = Time slot contains valid PCM data)
Slot 1
Slot 2
Slot 3
Slot 12
12.228 MHz
81.4 nS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI3012-KSR | 制造商:Silicon Laboratories Inc 功能描述: |
| SI-3012KS-TL | 制造商:Sanken Electric Co Ltd 功能描述:IC REG LDO ADJ 1A 8SOIC |
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| SI-3012LU-TL | 制造商:Sanken Electric Co Ltd 功能描述:IC REG LDO ADJ 0.25A SOT89-5 |
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