參數(shù)資料
型號(hào): SAA7708H
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)字信號(hào)處理
英文描述: Car Radio Digital Signal Processor
中文描述: 汽車無線電數(shù)字信號(hào)處理器
文件頁數(shù): 48/60頁
文件大?。?/td> 281K
代理商: SAA7708H
1998 May 19
48
Philips Semiconductors
Preliminary specification
Car Radio Digital Signal Processor
SAA7708H
line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge
related clock pulse. Setup and hold times must be taken into account. A master receiver must signal an end of data to
the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event
the transmitter must leave the data line HIGH to enable the master to generate a stop condition. See Fig. 19.
20 I
2
C BUS FORMAT
20.1
Addressing
Before any data is transmitted on the I
2
C bus, the device which should respond is addressed first. The addressing is
always done with the first byte transmitted after the start procedure.
20.2
Slave address (A0 pin)
The CDSP acts as slave receiver or a slave transmitter. Therefore the clock signal SCL is only an input signal. The data
signal SDA is a bidirectional line. The CDSP slave address is shown in table Table 15.
Table 15
Slave address
The sub address bit A0 corresponds to the hardware address pin A0 which allows the device to have 2 different
addresses. The A0 input is also used in test mode as serial input of the test control block.
MSB
LSB
0
0
1
1
1
0
A0
R/W
Fig. 19 Acknowledge on the I
2
C bus.
1
2
7
8
9
S
s t a r t
c o n d i t i o n
DAT A
OUT PUT
BY
T RANSMI T T ER
DAT A
OUT PUT
BY
RECEI VER
SCL
F ROM
MAST ER
n o t
a c k n o wl e d g e
a c k n o wl e d g e
c l o c k
p u l s e
f o r
a c k n o wl e d g e me n t
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