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參數(shù)資料
| 型號(hào)： | SAA7708H |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Car Radio Digital Signal Processor |
| 中文描述： | 汽車無線電數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 32/60頁 |
| 文件大?。?/td> | 281K |
| 代理商： | SAA7708H |
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1998 May 19
32
Philips Semiconductors
Preliminary specification
Car Radio Digital Signal Processor
SAA7708H
10.15.4 B
UFFER INTERFACE
The RDS interface buffers 16 data bits. Every time 16 bits are received, the data line in pulled down and the buffer is
overwritten. The control microprocessor has to monitor the data line in at most every 13.5 msec. This mode is selected
by setting the rds_clkin I
2
C bit of the IIC_RDS_ConTrol register ($0FF3) (see Table 29) to “1”. In Fig. 15 the interface
signals from the RDS decoder and the microcomputer in buffer mode are shown. When the buffer is filled with 16 bit the
data line is pulled down. The data line will remain low until reading of the buffer is started by pulling down the clock line.
The first bit is clocked out. After 16 clock pulses the reading of the buffer is ready and the data line is set high until the
buffer is filled again. The microprocessor stops communication by pulling the line high. The data is written out just after
the clock high-low transition. The data is valid when the clock is high.
When a new 16 bit buffer is filled before the other buffer is read, that buffer will be overwritten and the old data is lost.
10.16 DSP Reset
The reset pin is active low and has an internal pull-up resistor. Between this pin and the VDDD ground a capacitor should
be connected to allow a proper switch on of the supply voltage. The capacitor value is such that the chip is in reset as
long as the power supply is not stabilised. A more or less fixed relationship between the DSP reset (pin) and the POM
(pin) time constant is obligatory. The voltage on the POM pin determines the current flowing in the DACs. At 0 V at the
POM pin the DAC currents are zero and so also the DACs output voltages. At the VDDA2 voltage the DAC currents are
at their nominal (maximal) value. Long before the DAC outputs get to their nominal output voltages, the DSP must be in
working mode to reset the output register therefore the DSP time constant must be shorter than the POM time constant.
For advised capacitors see the application diagram.
The reset has the following function:
the bits of the IAC control register are set to their prefix values
the bits of the IIC_SEL register are set to their prefix values
the DSP status registers are reset
the program counter is set to address $0000.
RDS_DATA
RDS_CLOCK
D0
D1
D2
D13
D14
D15
Tpb
Twb
Thb
Tlb
Block ready
Start reading data
Fig. 15 Interface signals RDS decoder and microcomputer
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| SAA7709/N107 | 制造商:PHILIPS-SEMI 功能描述: |
| SAA7709H/N103 | 功能描述:音頻 DSP DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAA7709H/N103,518 | 功能描述:音頻 DSP DIRAC-2 RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAA7709H/N103,557 | 功能描述:音頻 DSP DIGITAL SIGNAL RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAA7709H/N103/S420 | 功能描述:音頻 DSP Car radio Digital Signal Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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