參數(shù)資料
型號(hào): SAA7708H
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)字信號(hào)處理
英文描述: Car Radio Digital Signal Processor
中文描述: 汽車無(wú)線電數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 46/60頁(yè)
文件大小: 281K
代理商: SAA7708H
1998 May 19
46
Philips Semiconductors
Preliminary specification
Car Radio Digital Signal Processor
SAA7708H
19 I
2
C BUS CONTROL AND COMMANDS
19.1
Characteristics of the I
2
C Bus
The I
2
C bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line
(SDA) and a serial clock line (SCL). Both lines must be connected to the VDD via a pull-up resistor when connected to
the output stages of a micro controller. For a 400 kHz I
2
S the recommendation for this type of bus from Philips
Semiconductors must be followed (e.g. up to loads of 200 pF on the bus a pull-up resistor can be used, between 200 -
400 pF a current source or switched resistor must be used). Data transfer can only be initiated when the bus is not busy.
19.2
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period
of the clock pulse as changes in the data line at this time will be interpreted as control signals. The maximum clock
frequency is 400 kHz. To be able to run on this high frequency all the In-Outputs connected to this bus must be designed
for this high speed I
2
C bus according the Philips specification. See Fig. 16.
19.3
Start and stop conditions
Both data and clock line will remain HIGH when the bus in not busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH, is defined as a start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is
defined as a stop condition (P). See Fig. 17.
Fig. 16 Bit transfer on the I
2
C bus
SDA
SCL
d a t a
l i n e
s t a b l e ;
d a t a
v a l i d
c h a n g e
o f
a l l o we d
d a t a
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