參數(shù)資料
型號: SAA7708H
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)字信號處理
英文描述: Car Radio Digital Signal Processor
中文描述: 汽車無線電數(shù)字信號處理器
文件頁數(shù): 2/60頁
文件大?。?/td> 281K
代理商: SAA7708H
1998 May 19
2
Philips Semiconductors
Preliminary specification
Car Radio Digital Signal Processor
SAA7708H
CONTENTS
1
2
3
4
5
6
7
8
9
9.1
10
10.1
10.1.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.3
10.4
10.5
10.6
10.7
10.7.1
10.7.2
10.7.3
10.7.4
10.7.5
10.7.6
10.7.7
10.7.8
10.7.9
10.7.10
10.7.11
10.7.12
10.8
10.8.1
10.8.2
10.8.3
10.8.4
10.8.5
10.8.6
10.8.7
10.8.8
10.9
GENERAL DESCRIPTION
HARDWARE FEATURES
SOFTWARE FEATURES
APPLICATIONS
QUICK REFERENCE DATA
ORDERING INFORMATION
APPLICATION BLOCK DIAGRAM
BLOCK DIAGRAM
PINNING
Pinning diagram
FUNCTIONAL DESCRIPTION
Signal path for Level information
The VREFAD pin
Signal path of the third order switched capacitor AD’s.
The FM MPX signal path
Input sensitivity for FM and RDS
The signal flow of the AM, CD analog and TAPE
Analog source switching
The realisation of common mode inputs
Phone input with volume control
Input selection switches
Supply of the analog inputs
The DCS clock block
Synchronization with the DSP core
IAC
General description
Parameter setting for the MPX input ignition detector
AGC set point (1 bit)
Threshold sensitivity offset (3 bits)
Deviation feed forward factor (3 bits)
Suppresion stretch time (3 bits)
MPX delay
Level IAC threshold (4 bits)
Level IAC feed forward setting (2 bits)
Level IAC suppression stretch time (2 bits)
Dynamic IAC threshold levels
IAC testing
Analog outputs
D/A converters
Upsample filter
Volume control
Function of the POM pin
The Fader
Power off plop suppression
The Internal VREFDA pin
Supply of the analog outputs
Clock circuit and oscillator
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