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1998 May 19
25
Philips Semiconductors
Preliminary specification
Car Radio Digital Signal Processor
SAA7708H
10.9.1
S
UPPLY OF THE
X-
TAL OSCILLATOR
The power supply connections of the oscillator are separate from the other supply lines. This to minimize the feedback
from the ground bounce of the chip to the oscillator circuit. The VSS_OSC pin is used as ground supply and the
VDD_OSC as positive supply.
10.10 The phase lock loop circuit to generate the DSP and other clocks
There are several reasons why two PLL circuits to generate the DSP clock and other clocks are used:
PLL1 is used to deliver the clock to the DSP core. The deviding factor of this PLL can be changed with I2C bits
PLL_DIV(3,2,1,0) but should only be used in the default position to ensure maximum functionality.
Crystals for the crystal oscillator in the range of twice the required DSP clock frequency, so approximately 45 MHz, are
always third overtone crystals and must also be fabricated on customer demand. This makes these crystals expensive.
The PLL2 enables the use of a crystal running in the fundamental mode and also a general available crystal can be
chosen. For this circuit a 256 X 44.1 kHz = 11.2896 MHz crystal is chosen. The clock of this PLL2 is used via a sample
rate converter for the AD decimation paths and stereo decoding, the SPDIF logic, the uProcessor interface and the
Fader DAC upsample filters.
With the I
2
C bit dsp_turbo (bit 11 of $0FFD) the output frequency can be doubled for test purposes by switching this bit
to 1, in functional mode only the default ‘0’ position is allowed.
10.11 The DSP core
For this chip a type of DSP core (the actual programmable embedded calculating machine) is used that is adapted to the
required calculation power needed and as such is optimized on area. This DSP core is also known under the name
EPICS6, of which EPICS is the generic name of this type of DSP and 6 is the version number. This DSP is mainly a
calculator designed for real time processing of the digitized (at 38 or 44.1 kHz sample frequency) audio data stream. A
DSP is especially suited to calculate the sum of products of the digital datawords representing the audio data.
10.12 DSP core status register and the external control pins
In the DSP core there is a 9 bit long status register. These 9 flags contain information which is used by the conditional
branch logic of the DSP core. For direct use with the external world 4 flags are defined, F0, F1, F2 and F3. For external
control two input pins, DSP_IN1 and DSP_IN2, have been implemented. These pins control the status of the flags F0
and F1. The two status flags F3 and F4 are controlled by the DSP core and can be read via the output pins DSP_OUT1
and DSP_OUT2. The functions of each pin depends on the DSP program. Another important flag is the I-flag. This flag
is an input flag and is set the moment new I
2
S data or another type of digital audio data is available to the DSP core.
10.13 I
2
C control (SCL and SDA pin)
General description of the I
2
C format in a booklet can be obtained at Philips Semiconductors, International Marketing
and Sales.
For the external control of the CDSP chip a fast I
2
C bus is implemented. This is a 400 kHz bus which is downward
compatible with the standard 100 kHz bus. There are three different types of control instructions:
Instructions to control the DSP program, programming the coefficient RAM and reading the values of parameters.
(level, multipath etc.)
Instructions controlling the DATA I
2
S flow, like source selection, IAC control and clock speed
The detailed description of the I
2
C bus and the description of the different bits in the memory map is given in paragraph:
I
2
C Bus control and commands.