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參數(shù)資料
| 型號(hào)： | SAA7392 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Channel encoder/decoder CDR60(通道編碼器/譯碼器) |
| 中文描述： | 信道編碼器/解碼器CDR60（通道編碼器/譯碼器） |
| 文件頁(yè)數(shù)： | 62/76頁(yè) |
| 文件大?。?/td> | 246K |
| 代理商： | SAA7392 |
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2000 Mar 21
62
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.17.7
ATIP S
TATUS
R
EGISTER
(ATIPS
TATUS
)
Table 143
ATIP Status Register (address 29H) - READ
Table 144
Description of ATIPStatus bits
7.17.8
W
OBBLE
F
REQUENCY
R
EGISTER
1 (W
OBBLE
F
REQ
1)
Table 145
Wobble Frequency Register 1 (address 2AH) - WRITE/READ
Table 146
Description of WobbleFreq1 bits
7.17.9
W
OBBLE
F
REQUENCY
R
EGISTER
2 (W
OBBLE
F
REQ
2)
Table 147
Wobble Frequency Register 2 (address 2BH) - READ/WRITE
Table 148
Description of WobbleFreq2 bits
7
6
5
4
3
2
1
0
ATIPReady
Busy
CRCOK
SyncErr
OIS
BIT
SYMBOL
DESCRIPTION
7
ATIPReady
If ATIPReady = 0, then ATIP data is not ready. If ATIPReady = 1, then ATIP data is ready
for read. Can also be an interrupt source.
If Busy = 0, then ATIP data is not being read. If Busy = 1, then sub-CPU is busy reading
ATIP data.
If CRCOK = 0, then CRC check is not OK. If CRCOK = 1, then CRC check is OK.
These 3 bits are reserved.
6
Busy
5
4
3
2
1
CRCOK
SyncErr
If SyncErr = 1, then detected sync is not in-phase with the interpolated sync. Resync will
be done on next detected sync.
If OIS = 1, then sync has been interpolated, no detected sync.
0
OIS
7
6
5
4
3
2
1
0
PLLFreq.15
PLLFreq.14
PLLFreq.13
PLLFreq.12
PLLFreq.11
PLLFreq.10
PLLFreq.9
PLLFreq.8
BIT
SYMBOL
DESCRIPTION
7 to 0
PLLFreq<15:8>
These 8 bits form the most significant byte of the PLL frequency.
7
6
5
4
3
2
1
0
PLLFreq.7
PLLFreq.6
PLLFreq.5
PLLFreq.4
PLLFreq.3
PLLFreq.2
PLLFreq.1
PLLFreq.0
BIT
SYMBOL
DESCRIPTION
7 to 0
PLLFreq<7:0>
These 8 bits form the least significant byte of the PLL frequency.
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