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參數(shù)資料
| 型號： | SAA7392 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Channel encoder/decoder CDR60(通道編碼器/譯碼器) |
| 中文描述： | 信道編碼器/解碼器CDR60（通道編碼器/譯碼器） |
| 文件頁數(shù)： | 47/76頁 |
| 文件大小： | 246K |
| 代理商： | SAA7392 |
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2000 Mar 21
47
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.12
The subcode insert function
The SAA7392 allows two modes of subcode insertion:
Bypass mode and Auto-format mode.
Bypass mode.
In this mode the subcode is generated
by a block decoder (such as PLUM) and transmitted to
the SAA7392 via the proprietary Subcode Record
Interface (SRI). P, Q and R to W channels are
supported in this mode. However, the Q-channel CRC
and the S0 and S1 bytes are generated by the
SAA7392. The Q-channel CRC is calculated from the
SRI data Q-bits and hence the 16 Q-channel CRC bits
in the SRI data are discarded.
Auto-format mode.
In this mode, the SAA7392 will
generate subcode data itself. However, only
P and Q subcode channels are supported.
It is possible to begin subcode recording at any point in the
subcode frame, for both internally and externally
generated subcode, by loading the preset count field (bits
PCF<6:0> in the SubPresetCount register) with the start
position in the subcode frame and setting the init_frame bit
to a logic 1.
It must be ensured that, if used, the external block encoder
is ready to transmit subcode data before the frame
initialisation is started. When the frame initialisation
sequence is complete the init_frame bit is automatically
cleared to a logic 0.
It should be noted that the frame initialisation sequence
must be carried out at the beginning of every record
session, even if starting from byte 0.
7.12.1
S
UBCODE
P
RESET
C
OUNT
R
EGISTER
(S
UB
P
RESET
C
OUNT
)
The preset count field is loaded when this register is written. The current count field is returned when this register is read.
Table 94
Subcode Preset Count Register (address 22H) - WRITE
Table 95
Subcode Preset Count Register (address 22H) - READ
7
6
5
4
3
2
1
0
init_frame
PCF.6
PCF.5
PCF.4
PCF.3
PCF.2
PCF.1
PCF.0
7
6
5
4
3
2
1
0
init_frame
CCF.6
CCF.5
CCF.4
CCF.3
CCF.2
CCF.1
CCF.0
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