參數(shù)資料
型號(hào)： SAA7392
廠商： NXP Semiconductors N.V.
英文描述： Channel encoder/decoder CDR60(通道編碼器/譯碼器)
中文描述： 信道編碼器/解碼器CDR60（通道編碼器/譯碼器）
文件頁數(shù)： 21/76頁
文件大?。?/td> 246K
代理商： SAA7392
2000 Mar 21
21
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.5.2
MEAS1
PIN
The MEAS1 pin carries the 3 measurement signals: jitter
(sampled twice), PLL frequency, and asymmetry. Each
frame consists of 64 bits (each 4 system clock periods
long), beginning with a start bit, then data bits then pause
bits (see Fig.8). The start bit is always preceded by
17 pause bits; and the intermediate start bits at
locations 12, 24 and 36 guarantee that no other ‘1’ bit is
preceded by 17 ‘0’ bits, making the start detection easy.
The structure of the frame is described in Table 23 and
shown in Fig.8.
Table 23
Frame structure
BIT
VALUE
FUNCTION
0
1 to 10
11
12
13 to 22
23
24
25 to 32
33
34
37 to 46
logic 1
jitter<9:0>
logic 0
logic 1
pllfreq<9:0>
logic 0
logic 1
assym<7:0> asymmetry word
logic 0
logic 1
intermediate start bit
jitter<9:0>
second sample of jitter
word
logic 0
pause
start bit
jitter word
intermediate start bit
PLL frequency word
intermediate start bit
47 to 63
Fig.8 Format on MEAS1 pin.
MGR798
handbook, halfpage
bit 0
bit 1
start
bit
pause
data bits
bit 2
bit 3
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