參數(shù)資料
型號(hào): SAA6703AH
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 顯示控制器
英文描述: CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160
封裝: 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160
文件頁(yè)數(shù): 87/97頁(yè)
文件大?。?/td> 488K
代理商: SAA6703AH
2004 Apr 01
88
Philips Semiconductors
Product specication
XGA analog input at panel controller
SAA6703AH
Notes
1. 1024
× 768 at 60 Hz with input pattern Grill_33.
2. Pin connected to video source via a 6 dB/75
attenuator.
3. Leakage current due to external voltage higher than internal VDD.
4. Minimum value for Vi = 4.5 V; maximum value for Vi = 5.5 V.
12 TIMING CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock input at pin CLK
Tcy
system clock cycle time
20
41.66
ns
Analog video interface; see Fig.33
Tcy
analog video clock cycle time
9.1
ns
tsu
video data set-up time
4
ns
th
video data hold time
3
ns
tVSYNC
vertical sync length
2/fVCLK
ns
tHSYNC
horizontal sync length
2/fVCLK
ns
Parallel video interface; see Fig.34
Tcy
parallel video clock cycle time
9.1
ns
tsu
video data set-up time
0
ns
th
video data hold time
5
ns
Panel interface; see Fig.35
Tcy
panel clock cycle time
15.4
40
ns
tout1
undelayed PCLK to output delay
time; single pixel mode
CL =15pF
2.5
+0.2
ns
tout2
undelayed PCLK to output delay
time; double pixel mode
CL =15pF
3.5
0.8
ns
tdel
output delay increment
200
500
800
ps
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