參數(shù)資料
型號: SAA6703AH
廠商: NXP SEMICONDUCTORS
元件分類: 顯示控制器
英文描述: CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160
封裝: 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160
文件頁數(shù): 42/97頁
文件大小: 488K
代理商: SAA6703AH
2004 Apr 01
47
Philips Semiconductors
Product specication
XGA analog input at panel controller
SAA6703AH
handbook, full pagewidth
MHB253
VHS
RGB data
h_offset
h_length
0
1
2
3
4
5
n
Fig.12 RGB data sampling (hsync_edge = 0).
handbook, full pagewidth
MHC220
VCLK
PA,
PB,
PC
HSYNC
X
6
5
4
3
2
1
0
X
in_h_offset
in_h_length
Fig.13 RGB input port timing using a data enable signal (connected to HSYNC).
7.8.4
INTERLACED INPUT
Sampling of interlaced RGB data is enabled by
interlace_on. The polarity of the input fields is determined
by the number of hsyncs within a frame. The even fields
are expected to contain an additional line if
reverse_field_id is set to logic 0, or to contain one line less
if reverse_field_id is set to logic 1.
In the interlaced input mode, the vertical sampling length
parameter in_v_length has to be programmed with the
length of the actual field (is half the frame length).
For de-interlacing, the upscaler has to be programmed
accordingly.
7.8.5
PICTURE GENERATOR
The input interface contains a picture generator, that can
be used to apply simple test pictures instead of using the
ADC. A front-end clock has to be provided
(see Section 7.4.1).
The picture generator is active when test_pic_on is logic 1.
It generates a picture of the size defined by in_h_length
and in_v_length with additional blanking. The total line
length and number of lines are defined by h_length_total
and v_length_total. The input interface sample offset is
without effect when using the picture generator.
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