參數(shù)資料
型號： SAA6703AH
廠商： NXP SEMICONDUCTORS
元件分類： 顯示控制器
英文描述： CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160
封裝： 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160
文件頁數(shù)： 44/97頁
文件大?。?/td> 488K
代理商： SAA6703AH
2004 Apr 01
49
Philips Semiconductors
Product specication
XGA analog input at panel controller
SAA6703AH
7.9
Colour processing
The colour processing performs brightness and contrast
adjustment. A programmable offset and gain factor is
applied to each RGB colour component. Additional gain
and offset values can be applied to the pixel data, not
affecting R, G and B components separately, but all
components at the same time. Luminance and
chrominance of the pixel data can be directly adjusted,
which allows true brightness, contrast and colour
saturation using single parameters. Register CP_GAIN_Y
controls the contrast and CP_OFFS_Y controls the
brightness level; both without affecting the colour
temperature. Registers CP_GAIN_CB, CP_OFFS_CB,
CP_GAIN_CR and CP_OFFS_CR specify gain and offset
values for the red and blue saturation of the RGB data. The
colour saturation can be shifted simply by using both gain
values.
The gain and offset values are specified by the 8-bit
configuration registers CP_GAIN_Y to CP_OFFS_B
(address 00H to 0BH at page 5). The offset values
offset_y, offset_cb and offset_cr for Y-CB-CR and offset_r,
offset_g and offset_b for RGB colour space are given in
the range from
128 (80H) to +127 (7FH) in
2s-complement form. The gain factors gain_y, gain_cb
and gain_cr as well as gain_r, gain_g and gain_b are given
in unsigned form, 128 (80H) representing a factor of 1.0.
7.10
RGB mode detection and auto-adjustment
The SAA6703AH can be used to build up auto-scan
systems using an external microcontroller. Therefore,
information about the input resolution and timing are
measured by the SAA6703AH that can be read out via the
I2C-bus.
Provided information can be divided into mode detection
information to determine the actual RGB input mode and
various auto-adjustment features to support the
adjustment of the setting of the SAA6703AH to the new
mode.
7.10.1
MODE DETECTION
The mode detection determines mode characteristics of
the selected video input. The information is provided at the
readable I2C-bus registers and changes in the values can
trigger the interrupt. All the mode detection I2C-bus
registers are mapped to register page 2. The mode
detection uses the back-end clock and cannot run without
a present back-end clock. The mode detection is enabled
by setting md_on to logic 1.
The source of the synchronization pulse signals used by
the mode detection is selected by the sync distribution as
described in Section 7.5.4 (HS_MDD and VS_MDD).
The absence of synchronization pulses is indicated by the
flags no_vsync and no_hsync. If the corresponding
synchronization signal cannot be detected, the flags are
set to logic 1; otherwise to logic 0. It should be noted that
the hsync is considered undetected, whenever there are
more than 65536 back-end clock cycles between two
hsyncs.
The bits vsync_pol and hsync_pol provide the polarities of
the synchronization signals applied. If the synchronization
signal is active HIGH, the corresponding flag is set to
logic 1; otherwise the flag is set to logic 0.
The flag jitter_detected is set to logic 1, when the active
edge of hsync and vsync coincide indicating a possible
jitter of the syncs, which would lead to an incorrect or
unstable result for the number of hsyncs between vsyncs;
otherwise the flag is set to logic 0. If a possible jitter
between hsync and vsync is detected, a delayed vsync
can be used for the measurements instead, which is
selected by setting delay_vsync to logic 1; otherwise the
original vsync is used.
The value of v_lines reports the number of lines within a
frame up to a maximum of 2048 lines and v_clocks gives
the length of the input frame in back-end clock cycles with
a maximum of 224 clock cycles. The horizontal period in
back-end clock cycles is given by h_clocks, which can be
determined in different measurement modes.
If h_clocks_accu and h_clocks_cont are both set to
logic 0, the h_clocks value is determined once per frame in
the middle of the frame. If h_clocks_accu is logic 1, then
h_clocks gives the accumulated length of 16 lines also
measured in the middle of the frame. If h_clocks_accu is
logic 0, but h_clocks_cont is set to logic 1, then the
h_clocks measurement is performed every line of the
frame, including the vertical blanking and vsync time. The
maximum horizontal period is 65536 back-end clock
cycles.
The measurement results can be used to generate a mode
detection interrupt. Each flag or value can be individually
enabled for interrupt generation by setting the
corresponding interrupt enable bit jitter_int_en,
v_lines_int_en, h_clocks_int_en, v_clocks_int_en,
no_vsync_int_en, no_hsync_int_en, vsync_pol_int_en or
hsync_pol_int_en to logic 1. Changes of v_lines, v_clocks
and h_clocks only cause an interrupt if the difference
between new and old value is greater than four.
相關PDF資料
PDF描述
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