參數(shù)資料
型號(hào): SAA6703AH
廠商: NXP SEMICONDUCTORS
元件分類: 顯示控制器
英文描述: CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160
封裝: 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160
文件頁(yè)數(shù): 8/97頁(yè)
文件大小: 488K
代理商: SAA6703AH
2004
Apr
01
16
Philips
Semiconductors
Product
specication
XGA
analog
input
at
panel
controller
SAA6703AH
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Note
1. X = don’t care.
Table 8
ADC conguration registers (page 1)
SYNC_DIS
19H W
000 0000
reserved
mdd_cs_
sog_en
mdd_hs_
regen_on
reserved
iif_cs_sog_
en
iif_hs_
regen_on
PLL programming: 20H to 29H
CD_PLL_CTRL
20H W
010 000
line_pll_
hs_pol
line_pll_
vs_pol
line_pll_en
pll_src
pll_pre_
div_en
pll_en
CD_PLL_P_HI
21H W
00H
pll_pre_div[15:8]
CD_PLL_P_LO
22H W
00H
pll_pre_div[7:0]
CD_PLL_HI
23H W
00 0000
pll_m_div[1:0]
pll_n_div[11:8]
CD_PLL_LO
24H W
00H
pll_n_div[7:0]
CD_LPLL_HI
25H W
00 0000
line_pll_m_div[1:0]
line_pll_n_div[11:8]
CD_LPLL_LO
26H W
00H
line_pll_n_div[7:0]
CD_LPLL_PHA
27H W
0 0000
line_pll_phase[4:0]
CD_LPLL_PD
28H W
100 0000
phase_
auto
phase_
select
pd_pll_phase[4:0]
CD_PLL_LOCK
29H R
XXX
phase_
inlock
pll_inlock
llpll_inlock
Interface timing: 34H and 35H
IT_CTRL
34H W
11
adc_pon_
pol
bigger_
out_pol
IT_PLL
35H W
1111
pll_coast_
pol
pll_pon_pol llpll_coast_
pol
llpll_pon_
pol
REGISTER
ADR R/W
RESET
D7
D6
D5
D4
D3
D2
D1
D0
ADC programming: 00H to 06H
ADC_CTRL
00H W
000
sog_vs_
disable
reserved
sync_on_
green_en
ADC_R_BRI
01H W
00H
adc_red_brightness[7:0]
ADC_R_CON
02H W
00H
adc_red_contrast[7:0]
ADC_G_BRI
03H W
00H
adc_green_brightness[7:0]
REGISTER
ADR R/W
RESET
D7
D6
D5
D4
D3
D2
D1
D0
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