- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄385800 > S29GL128M90FAIR20 (SPANSION LLC) MOSFET, Switching; VDSS (V): -30; ID (A): -14; Pch : 2.5; RDS (ON) typ. (ohm) @10V: 0.009; RDS (ON) typ. (ohm) @4V[4.5V]: [0.015]; RDS (ON) typ. (ohm) @2.5V: -; Ciss (pF) typ: 3500; toff (µs) typ: 0.31; Package: SOP-8 PDF資料下載
參數(shù)資料
| 型號(hào)： | S29GL128M90FAIR20 |
| 廠商： | SPANSION LLC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | MOSFET, Switching; VDSS (V): -30; ID (A): -14; Pch : 2.5; RDS (ON) typ. (ohm) @10V: 0.009; RDS (ON) typ. (ohm) @4V[4.5V]: [0.015]; RDS (ON) typ. (ohm) @2.5V: -; Ciss (pF) typ: 3500; toff (µs) typ: 0.31; Package: SOP-8 |
| 中文描述： | 8M X 16 FLASH 3V PROM, 90 ns, PBGA64 |
| 封裝： | 13 X 11 MM, FORTIFIED, BGA-64 |
| 文件頁(yè)數(shù)： | 104/160頁(yè) |
| 文件大?。?/td> | 2142K |
| 代理商： | S29GL128M90FAIR20 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)當(dāng)前第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)
104
S29GLxxxM MirrorBit
TM
Flash Family
S29GLxxxM_00A5 April 30, 2004
P r e l i m i n a r y
reinitiated once the device has returned to the read mode, to ensure data
integrity.
Programming is allowed in any sequence of address locations and across sector
boundaries. Programming to the same word address multiple times without in-
tervening erases (incremental bit programming) requires a modified
programming method. For such application requirements, please contact your
local Spansion representative. Word programming is supported for backward
compatibility with existing Flash driver software and for occasional writing of in-
dividual words. Use of write buffer programming (see below) is strongly
recommended for general programming use when more than a few words are to
be programmed. The effective word programming time using write buffer pro-
gramming is approximately four times shorter than the single word programming
time.
Any bit in a word cannot be programmed from “0” back to a “1.”
Attempt-
ing to do so may cause the device to set DQ5=1, or cause DQ7 and DQ6 status
bits to indicate the operation was successful. However, a succeeding read will
show that the data is still “0.” Only erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device
faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass mode command
sequence is all that is required to program in this mode. The first cycle in this se-
quence contains the unlock bypass program command, A0h; the second cycle
contains the program address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two unlock cycles required in
the standard program command sequence, resulting in faster total programming
time. Tables 31 and 32 show the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-
pass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first cycle
must contain the data 90h. The second cycle must contain the data 00h. The de-
vice then returns to the read mode.
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/32
bytes in one programming operation. This results in faster effective programming
time than the standard programming algorithms. The Write Buffer Programming
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the Write Buffer Load command written at the
Sector Address in which programming will occur. The fourth cycle writes the sec-
tor address and the number of word locations, minus one, to be programmed. For
example, if the system will program 6 unique address locations, then 05h should
be written to the device. This tells the device how many write buffer addresses
will be loaded with data and therefore when to expect the Program Buffer to Flash
command. The number of locations to program cannot exceed the size of the
write buffer or the operation will abort.
The fifth cycle writes the first address location and data to be programmed. The
write-buffer-page is selected by address bits A
MAX
–A
4
. All subsequent address/
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29GL128M90FAIR22 | 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology |
| S29GL128M90FAIR23 | MOSFET, Switching; VDSS (V): -60; ID (A): -5; Pch : 2.0/3.0; RDS (ON) typ. (ohm) @10V: 0.06; RDS (ON) typ. (ohm) @4V[4.5V]: [0.09]; RDS (ON) typ. (ohm) @2.5V: -; Ciss (pF) typ: 1350; toff (µs) typ: 0.055; Package: SOP-8 |
| S29GL128M90FAIR80 | MOSFET, Switching; VDSS (V): -60; ID (A): -5; Pch : 2.0/3.0; RDS (ON) typ. (ohm) @10V: 0.06; RDS (ON) typ. (ohm) @4V[4.5V]: [0.09]; RDS (ON) typ. (ohm) @2.5V: -; Ciss (pF) typ: 1350; toff (µs) typ: 0.055; Package: SOP-8 |
| S29GL128M90FAIR82 | 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology |
| S29GL128M90FAIR83 | 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29GL128M90TAIR10 | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 128M-Bit 16M x 8/8M x 16 90ns 56-Pin TSOP Tray |
| S29GL128M90TAIR13 | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 16MX8/8MX16 90NS 56TSOP - Tape and Reel |
| S29GL128M90TFIR10 | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 128M-Bit 16M x 8/8M x 16 90ns 56-Pin TSOP Tray |
| S29GL128N10FFI010 | 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 128Mbit 16M/8M x 8bit/16bit 100ns 64-Pin Fortified BGA Tray 制造商:Spansion 功能描述:MIRRORBIT FLASH 128MB SMD 29LV128 |
| S29GL128N10FFI020 | 制造商:Spansion 功能描述:Flash - NOR IC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。