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參數(shù)資料
| 型號(hào)： | S1C62920D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC63 |
| 封裝： | DIE-63 |
| 文件頁(yè)數(shù)： | 68/78頁(yè) |
| 文件大?。?/td> | 874K |
| 代理商： | S1C62920D |
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62
EPSON
S1C62920 TECHNICAL MANUAL
CHAPTER 5: SUMMARY OF NOTES
(3) When using the OSC3 clock as the time base counter input clock, the OSC3 oscillation circuit must be
ON (OSCC = "1") before starting R/F conversion.
It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabilizes.
Consequently, when starting a remote output, secure 5 msec or more waiting time for oscillation
stabilization after turning the OSC3 oscillation ON.
Further, the oscillation stabilization time varies depending on the external oscillator characteristics and
conditions of use, so allow ample margin when setting the waiting time.
SVD circuit
(1) To obtain a stable SVD detection result, the SVD circuit must be on for at least l00 sec. So, to obtain the
SVD detection result, follow the programming sequence below.
Set SVDON to "1"
Maintain for 100 sec minimum
Set SVDON to "0"
Read SVDDT
However, when fOSC1 is selected for CPU system clock, the instruction cycles are long enough, so there
is no need to worry about maintaining 100 sec for SVDON = "1" in the software.
(2) The SVD circuit should normally be turned OFF as the consumption current of the IC becomes large
when it is ON.
Interrupt and HALT
(1) The interrupt factor flags are set when the timing condition is established, even if the interrupt mask
registers are set to "0".
(2) Reading of interrupt factor flag is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will
not be generated.
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