S1C62920 TECHNICAL MANUAL
EPSON
33
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
Fig. 4.8.3.1 Timing chart of clock timer
As shown in Figure 4.8.3.1, interrupt is generated at the falling edge of the frequencies (32 Hz, 8 Hz, 2 Hz).
At this time, the corresponding interrupt factor flag (IT0, IT1, IT2) is set to "1". Selection of whether to mask
the separate interrupts can be made with the interrupt mask registers (EIT0, EIT1, EIT2). However, regard-
less of the interrupt mask register setting, the interrupt factor flag is set to "1" at the falling edge of the
corresponding signal.
4.8.4 Control of clock timer
Table 4.8.4.1 shows the clock timer control bits and their addresses.
Table 4.8.4.1 Control bits of clock timer
Address
Comment
Register
D3
D2
D1
D0
Name
Init
1
0
*1
TMRST
W
TM0
TM4
EIT0
IT0
R
0
TMRUN
TMRST
TM3
TM2
TM1
TM0
TM7
TM6
TM5
TM4
0
EIT2
EIT1
EIT0
0
IT2
IT1
IT0
–
0
Reset
0
–
0
–
0
Run
Reset
Enable
Yes
Stop
–
Mask
No
TMRUN
R/W
TM1
TM5
EIT1
R/W
IT1
0
TM2
TM6
EIT2
IT2
0
TM3
TM7
0
R
0
C8H
C9H
CAH
F4H
FCH
*2
*5
*4
*7
Unused
Clock timer Run/Stop
Clock timer reset
Clock timer data (16 Hz)
Clock timer data (32 Hz)
Clock timer data (64 Hz)
Clock timer data (128 Hz)
Clock timer data (1 Hz)
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
Unused
Interrupt mask register (Clock timer 2 Hz)
Interrupt mask register (Clock timer 8 Hz)
Interrupt mask register (Clock timer 32 Hz)
Unused
Interrupt factor flag (Clock timer 2 Hz)
Interrupt factor flag (Clock timer 8 Hz)
Interrupt factor flag (Clock timer 32 Hz)
R
*1 Initial value at the time of initial reset
*5 Constantly "0" when being read
*2 Not set in the circuit
*6 Refer to main manual
*3 Undefined
*7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
Clock timer timing chart
Frequency
Register
Address
CAH
D3
D0
D1
D2
4 Hz
2 Hz
8 Hz interrupt request
C9H
2 Hz interrupt request
D3
1 Hz
D0
D1
D2
128 Hz
16 Hz
8 Hz
32 Hz
64 Hz
(When fOSC1 = 32.768 kHz)
32 Hz interrupt request