參數(shù)資料
型號(hào)： S1C62920D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC63
封裝： DIE-63
文件頁(yè)數(shù)： 6/78頁(yè)
文件大?。?/td> 874K
代理商： S1C62920D
6
EPSON
S1C62920 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.1.1 Voltage <VD1> for oscillation circuit and internal circuits
VD1 is the voltage for the oscillation circuit and the internal logic circuits, and is generated by the oscillation
system regulated voltage circuit for stabilizing the oscillation.
Making VSS the standard (GND level), the oscillation system regulated voltage circuit generates VD1 from
the supply voltage that is input from the VDD–VSS terminals.
2.1.2 Voltage <VC1, VC2 and VC3> for LCD driving
VC1, VC2 and VC3 are the voltages for LCD drive, and are generated by the LCD system voltage boost/
reduction circuit to stabilize the display quality.
VC2 is generated by connecting the VC2 terminal to the VDD or VD1 terminal.
The LCD system voltage boost/reduction circuit generates VC1 and VC3 by transforming VC2 into 1/2 and
3/2, respectively.
The following shows VC1–VC3 voltages when VC2 is connected to the VDD terminal or the VD1 terminal :
Terminal connected to VC2
VC1
VC2
VC3
(Recommended operating conditions)
VDD terminal
1/2 VDD
VDD
3/2 VDD
(VDD = 2.2 to 3.6 V)
VD1 terminal
approx. 1 V
approx. 2 V
approx. 3 V
(VDD = 2.2 to 5.5 V)
2.2 Initial Reset
To initialize the S1C62920 circuits, initial reset must be executed. There are two ways of doing this.
(1) External initial reset by the RESET terminal
(2) Initial reset by the watchdog timer
Be sure to use reset function (1) when turning the power on and be sure to initialize securely. In normal
operation, the circuit may be initialized by any of the above two types.
Figure 2.2.1 shows the configuration of the initial reset circuit.
OSC1
OSC2
OSC1
oscillation
circuit
fOSC1
Dividing circuit
1 Hz
2 Hz
Watchdog
timer
R
S
Q
Internal
initial
reset
VDD
RESET
Fig. 2.2.1 Configuration of the initial reset circuit
2.2.1 Reset terminal (RESET)
Initial reset can be executed externally by setting the reset terminal to a low level (VSS). After that the initial
reset is released by setting the reset terminal to a high level (VDD) and the CPU starts operation.
The reset input signal is maintained by the RS latch and becomes the internal initial reset signal. The RS
latch is designed to be released by a 2 Hz signal (high) that is divided by the OSC1 clock. Therefore in
normal operation, a maximum of 250 msec (when fOSC1 = 32 kHz) is needed until the internal initial reset is
released after the reset terminal goes to high level. Be sure to maintain a reset input of 0.1 msec or more.
However, when turning the power on, the reset
terminal should be set at a low level as in the
timing shown in Figure 2.2.1.1.
VDD
RESET
2.0 msec or more
2.2 V
0.4VDD
0.1VDD or less (low level)
Power on
Fig. 2.2.1.1 Initial reset at power on
The reset terminal should be set to 0.1VDD or less
(low level) until the supply voltage becomes 2.2 V
or more.
After that, a level of 0.4VDD or less should be
maintained more than 2.0 msec.
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