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參數(shù)資料
| 型號： | S1C62920D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC63 |
| 封裝： | DIE-63 |
| 文件頁數(shù)： | 61/78頁 |
| 文件大?。?/td> | 874K |
| 代理商： | S1C62920D |
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56
EPSON
S1C62920 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
4.12.1 Interrupt factor
Table 4.12.1.1 shows the factors for generating interrupt requests.
The interrupt flags are set to "1" depending on the corresponding interrupt factors.
The CPU operation is interrupted when any of the conditions below set an interrupt factor flag to "1".
The corresponding mask register is "1" (enabled)
The interrupt flag is "1" (EI)
The interrupt factor flag is a read-only register, but can be reset to "0" when the register data is read out.
At initial reset, the interrupt factor flags are reset to "0".
Note: Reading of interrupt factor flag is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1",
an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request
will not be generated.
4.12.2 Interrupt mask
The interrupt factor flags can be masked by the corresponding interrupt mask registers.
The interrupt mask registers are read/write registers. They are enabled (interrupt authorized) when "1" is
written to them, and masked (interrupt inhibited) when "0" is written to them.
At initial reset, the interrupt mask register is set to "0".
Table 4.12.2.1 shows the correspondence between interrupt mask registers and interrupt factor flags.
4.12.3 Interrupt vector
When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program
being executed is terminated, the interrupt processing is executed in the following order.
The address data (value of program counter) of the program to be executed next is saved in the stack
area (RAM).
The interrupt request causes the value of the interrupt vector (page 1, 02H–0AH) to be set in the
program counter.
The program at the specified address is executed (execution of interrupt processing routine by soft-
ware).
Table 4.12.3.1 shows the correspondence of interrupt requests and interrupt vectors.
Note: The processing in and above take 12 cycles of the CPU system clock.
Table 4.12.1.1
Interrupt factors
Interrupt factor
Serial interface (data send/receive has completed)
R/F converter (R/F conversion has completed)
K00–K03 input (falling or rising edge)
Clock timer 2 Hz (falling edge)
Clock timer 8 Hz (falling edge)
Clock timer 32 Hz (falling edge)
Interrupt factor flag
ISIF
IRF
IK0
IT2
IT1
IT0
(F8HD0)
(F9HD0)
(FBHD0)
(FCHD2)
(FCHD1)
(FCHD0)
Table 4.12.2.1
Interrupt mask registers and
interrupt factor flags
Interrupt mask register
Interrupt factor flag
ISIF
IRF
IK0
IT2
IT1
IT0
(F8HD0)
(F9HD0)
(FBHD0)
(FCHD2)
(FCHD1)
(FCHD0)
EISIF
EIRF
EIK0
EIT2
EIT1
EIT0
(F0HD0)
(F1HD0)
(F3HD0)
(F4HD2)
(F4HD1)
(F4HD0)
Interrupt request
Serial interface
R/F converter
K00–K03 input
Clock timer
Priority
High
↑
↓
Low
Interrupt vector
102H
104H
108H
10AH
Table 4.12.3.1
Interrupt request and
interrupt vectors
The four low-order bits of the program counter are indirectly addressed through the interrupt request.
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