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參數(shù)資料
| 型號： | S1C62920D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC63 |
| 封裝： | DIE-63 |
| 文件頁數(shù)： | 37/78頁 |
| 文件大?。?/td> | 874K |
| 代理商： | S1C62920D |
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34
EPSON
S1C62920 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
TM0–TM7: Timer data (C9H, CAH)
The 128 Hz–1 Hz timer data of the clock timer can be read out with these registers. These eight bits are read
only, and writing operations are invalid.
By reading the low-order data (C9H), the high-order data (CAH) is held while the shorter of the two
indicated here following.
1. Period until it reads the high-order data.
2. 0.48–1.5 msec (varies due to the timing of the reading)
At initial reset, the timer data is initialized to "00H".
TMRST: Clock timer reset (C8HD0)
This bit resets the clock timer.
When "1" is written:
Clock timer reset
When "0" is written:
No operation
Reading:
Always "0"
The clock timer is reset by writing "1" to TMRST. When the clock timer is reset in the RUN status, operation
restarts immediately. Also, in the STOP status the reset data is maintained. No operation results when "0" is
written to TMRST.
This bit is write-only, and so is always "0" at reading.
TMRUN: Clock timer RUN/STOP (C8HD1)
This bit controls RUN/STOP of the clock timer.
When "1" is written:
RUN
When "0" is written:
STOP
Reading:
Valid
The clock timer enters the RUN status when "1" is written to TMRUN, and the STOP status when "0" is
written.
In the STOP status, the timer data is maintained until the next RUN status or resets timer. Also, when the
STOP status changes to the RUN status, the data that was maintained can be used for resuming the count.
At initial reset, this register is set to "0".
EIT0, EIT1, EIT2: Interrupt mask registers (F4HD0, D1, D2)
These registers are used to select whether to mask the clock timer interrupt.
When "1" is written:
Enabled
When "0" is written:
Masked
Reading:
Valid
The interrupt mask registers (EIT0, EIT1, EIT2) are used to select whether to mask the interrupt to the
separate frequencies (32 Hz, 8 Hz, 2 Hz).
At initial reset, these registers are all set to "0".
IT0, IT1, IT2: Interrupt factor flags (FCHD0, D1, D2)
These flags indicate the status of the clock timer interrupt.
When "1" is read:
Interrupt has occurred
When "0" is read:
Interrupt has not occurred
Writing:
Invalid
The interrupt factor flags (IT0, IT1, IT2) correspond to the clock timer interrupts of the respective frequen-
cies (32 Hz, 8 Hz, 2 Hz). The software can judge from these flags whether there is a clock timer interrupt.
However, even if the interrupt is masked, the flags are set to "1" at the falling edge of the signal.
These flags can be reset through being read out by the software.
Reading of interrupt factor flags is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an
interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not
be generated.
At initial reset, these flags are set to "0".
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