9 STATE CONTROLLER
92
EPSON
S1C38000 TECHNICAL MANUAL
9 State Controller
9.1 Overview
The State Controller (STATE) contains five separate functions: Memory Re-mapping, Pause
Control, Reset Status Identification, Identification Register, and System Configuration Registers.
9.2 Memory Re-map
The write-only Clear Reset Map Register provides a method of overlaying the system base memory
and shuffling memory banks after reset. Writing (any value) to the Clear Reset Map register causes
the system memory map to change from the reset default to that specified by the address re-map
registers in the AHB decoder. A typical system implementation would be to map the system ROM to
address location 0 at reset, but to change it after reset such that RAM is located at address location 0
instead.
9.3 Pause
A write to the write-only Pause Register will cause the system to enter a wait-for-interrupt state. In
such a state, the processor is prevented from fetching further instructions until the receipt of an
interrupt or a power on reset. The wait-for-interrupt state can be a method to transit the S1C38000 to
Sleep/Suspend state by programming the power manager appropriately. Refer to Section 11, “Power
Manager” on page 98 for further information.
9.4 Reset
The Reset Status Register indicates the cause of the most recent reset condition.
The Reset Status Register is read only. The lower two bits of this register, the Power On Reset bit
and the Watchdog Timer reset bit, may be used to determine if the most recent reset was caused by
initial power on, or if a warm reset has occurred.
9.5 Register Descriptions
The default base address for the STATE registers is F8001000h. All non-reserved register bits
default to 0 unless specified otherwise.
bits 31–0
Pause
This is a write-only register that, when written to, causes the system to enter a wait-for-
interrupt state. The value written is a don’t-care.
Pause Register
SC[000h]
Write Only
Pause
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Pause
15
14
13
12
11
10
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