7 SYSTEM OVERVIEW
86
EPSON
S1C38000 TECHNICAL MANUAL
Memory
Interface
Controller
Base Address
F8000100h
SDRAM Initialization Register
MEM[00h]
R/W
32bit
APB
32bit
Device 0 Configuration Register
MEM[04h]
R/W
32bit
Device 1 Configuration Register
MEM[08h]
R/W
32bit
Device 2 Configuration Register
MEM[0Ch]
R/W
32bit
Device 3 Configuration Register
MEM[10h]
R/W
32bit
Device 4 Configuration Register
MEM[14h]
R/W
32bit
Device 5 Configuration Register
MEM[18h]
R/W
32bit
Real-Time Clock
Base Address
F8000140h
Start/Stop Control Register
RTC[00h]
R/W
8bit
APB
32bit
Interrupt Register
RTC[04h]
R/W
8bit
32bit
Timer Divide Register
RTC[08h]
R
8bit
32bit
Timer Second Register
RTC[0Ch]
R/W
8bit
32bit
Timer Minute Register
RTC[10h]
R/W
8bit
32bit
Timer Hour Register
RTC[14h]
R/W
8bit
32bit
Timer Day Register
RTC[18h]
R/W
16bit
32bit
Alarm Minute Register
RTC[20h]
R/W
8bit
32bit
Alarm Hour Register
RTC[24h]
R/W
8bit
32bit
Alarm Day Register
RTC[28h]
R/W
16bit
32bit
Reserved
RTC[2Ch]
R/W
8bit
32bit
DMA Controller
Base Address
F8000180h
Channel 0 Source Address Register
DMA[00h]
R/W
32bit
APB
32bit
Channel 0 Destination Address Register
DMA[04h]
R/W
32bit
Channel 0 Transfer Count Register
DMA[08h]
R/W
24bit
32bit
Channel 0 Control Register
DMA[0Ch]
R/W
32bit
Channel 1 Source Address Register
DMA[10h]
R/W
32bit
Channel 1 Destination Address Register
DMA[14h]
R/W
32bit
Channel 1 Transfer Count Register
DMA[18h]
R/W
24bit
32bit
Channel 1 Control Register
DMA[1Ch]
R/W
32bit
Channel 2 Source Address Register
DMA[20h]
R/W
32bit
Channel 2 Destination Address Register
DMA[24h]
R/W
32bit
Channel 2 Transfer Count Register
DMA[28h]
R/W
24bit
32bit
Channel 2 Control Register
DMA[2Ch]
R/W
32bit
Channel 3 Source Address Register
DMA[30h]
R/W
32bit
Channel 3 Destination Address Register
DMA[34h]
R/W
32bit
Channel 3 Transfer Count Register
DMA[38h]
R/W
24bit
32bit
Channel 3 Control Register
DMA[3Ch]
R/W
32bit
DMA Operation Register
DMA[40h]
R/W
16bit
32bit
Interrupt
Controller
Base Address
F8000200h
IRQ Status Register
IRQ[000h]
R
32bit
APB
32bit
IRQ Raw Status Register
IRQ[004h]
R
32bit
IRQ Enable Register
IRQ[008h]
R/W
32bit
IRQ Enable Clear Register
IRQ[00Ch]
W
32bit
Software IRQ Register
IRQ[010h]
W
8bit
32bit
IRQ Level Register
IRQ[080h]
R/W
32bit
IRQ Polarity Register
IRQ[084h]
R/W
32bit
IRQ Trigger Reset Register
IRQ[088h]
W
32bit
FIQ Status Register
IRQ[100h]
R
8bit
32bit
FIQ Raw Status Register
IRQ[104h]
R
8bit
32bit
FIQ Enable Register
IRQ[108h]
R/W
8bit
32bit
FIQ Enable Clear Register
IRQ[10Ch]
W
8bit
32bit
FIQ Level Register
IRQ[180h]
R/W
8bit
32bit
FIQ Polarity Register
IRQ[184h]
R/W
8bit
32bit
FIQ Trigger Reset Register
IRQ[188h]
W
8bit
32bit
Table 7-4 Register Access Table (Continued)
Device
Register
Address
Data
Type
Register
Size
Access
Type
Access
Size