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| 型號(hào)： | S1C38000B0A0100 |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, RISC MICROCONTROLLER, BGA239 |
| 封裝： | CFLGA-239 |
| 文件頁(yè)數(shù)： | 120/281頁(yè) |
| 文件大小： | 1309K |
| 代理商： | S1C38000B0A0100 |
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21 IRDA
192
EPSON
S1C38000 TECHNICAL MANUAL
bit 3
Transmit Data Writable
When this bit reads 1, the Transmit Data is Writable. There is space in the transmit FIFO
to write, and the number of transmission data length bytes are not written. When this bit
reads 0, the Transmit Data is not Writable. This indicates that the number of
transmission data length bytes are already written to the transmit FIFO. If all the bytes
are not written it indicates that the transmit FIFO is full.
bit 2
Transmit Underrun Error
When this bit reads 1, a Transmit Underrun Error has occurred. This error occurs when
not enough data is provided to the transmitter. An example of this is when the number of
writes to the transmit FIFO is less than the transmission data length bytes written to
IRDA[08h]. When this bit reads 0, no Transmit Underrun Error has occurred.
Note: Transmit DMA must be enabled.
bit 1
Carrier Sense
When this bit reads 1, the IrDA FIR demodulator sensed activity on the optical input.
When this bit reads 0, no activity is sensed on the optical input for two microseconds.
bit 0
Transmit End of Frame
When this bit reads 1, transmission of End of Frame has completed. When this bit reads
0, transmission of End of Frame did not complete.
Note: Transmit DMA must be enabled.
bit 15
Transmit Enable
When this bit is written 1, the transmit circuit of the device is enabled. The FIR
modulation circuit is active and data transmission can continue. When this bit is written
0, the transmit circuit in the device is disabled. The transmit circuit is initialized and the
clock to the FIR modulation circuit is switched off.
bit 14
Transmit CRC Enable
When this bit is written 1, CRC generation for the transmit circuit of the device is
enabled. Four bytes of CRC is added to the data being transmitted. When this bit is
written 0, CRC generation for the transmit circuit is disabled. Data is transmitted
without any CRC bytes.
bit 13
Receive Enable
When this bit is written 1, the receive circuit of the device is enabled. The FIR
demodulation circuit is active and data reception is active. When this bit is written 0, the
receive circuit of this device is disabled. The receive circuit is initialized and the clock
to the FIR demodulation circuit is stopped.
bit 12
Receive CRC Enable
When this bit is written 1, CRC operations are performed on the receive data, and the
status of the check is reported in the Receive Framing Error bit (IRDA[00h] RO bit 5).
When this bit is written 0, no CRC operations are performed on the receive data, and no
CRC error status is set.
IrDA Control Register 1
IRDA[04h]
Write Only
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Transmit
Enable
Transmit
CRC
Enable
Receive
Enable
Receive
CRC
Enable
Address
Search
Enable
Multicast
Enable
reserved
Receive
Overrun
Error
Mask
Receive
Framing
Error
Receive
End
Mask
Timer
Interrupt
Mask
Transmit
Underrun
Error
Mask
reserved
Transmit
End
Mask
15
14
13
12
11
10
9876543210
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參數(shù)描述 |
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| S1C-38-S | 制造商:GRIPCO 功能描述: |
| S-1-C-6.6-D D/C .670 OAL | 功能描述:觸點(diǎn)探頭 HEADLESS FLAT RoHS:否 制造商:IDI 類(lèi)型:Probes 尖端類(lèi)型:Spherical Radius 長(zhǎng)度:8.26 mm 電流額定值:10 A 彈力:2.3 oz 行程:1.52 mm 系列:101050 |
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